United Microelectronics Corp.

Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Mpi Corporation

Mosel Vitelic Corporation

Htc Corporation

Ace Cad Enterprise Co., Ltd.

National Yang Ming Chiao Tung University

Richtek Technology Corporation

Quanta Display Inc.

Hon Hai Precision Industry Co., Ltd.

Industrial Technology Research Institute

E Ink Holdings Inc.

Icf Technology Co., Ltd.

Chien-Hung Chen

Tzu-Ping Chen

Chun-Yuan Wu

Yu-Ru Yang

Shih-Hsien Huang

Che-Yu Lin

Huai-Tzu Chiang

Wen-Chu Hsiao

Cheng-Tzung Tsai

Han-Tu Lin

Shen-De Wang

Sheng-Hao Lin

Wen-Chung Chang

Shin-Puu Jeng

Yee-Chia Yeo

Po-Yao Lin

Hsueh-Chung Chen

Shu-Shen Yeh

Yu-Sheng Lin

Yi-Wei Lee

Hao-Ming Lee

Stojan Kanev

Chun-Liang Hou

Chien-Wei Lee

Chih-Yueh Li

Chen-Hsien Hsu

Wei-Jen Wang

Chien-Fu Chen

Kun-Yuan Wu

Ruei-Yau Chen

Yu-Hsun Hsu

Chun-Hsien Lin

Isaac Y Chen

Chin-Hua Wang

Chi-Mao Hung

Juan-Yuan Wu

I-Cheng Chuang

Chih-Jung Chen

Chin-Sheng Yang

Chih-Jen Huang

Mei-Sheng Ma

Ching-Yi Hsu

Jyun-Che Ho

Wei-Shang King

Cheng-Pu Chiu

Yeong-Feng Wang

Shui-Chin Huang

Wei-Sheng Yu

Cheng-Te Chen

Chia-Wen Wang

Chih-Chiang Chang

Chii-Horng Li

Ming-Hua Yu

Chien-Li Kuo

Li-Hsien Huang

Chun-Hsien Huang

Chih-Kai Hsu

Yao-Chun Chuang

Yi-Pai Huang

Yuan-Ching Peng

Wen-Jung Liao

Po-Chen Lai

Yu-Tse Kuo

Kai-Ming Ching

Jiun-Ming Kuo

Han-Ping D Shieh

Shu-Ru Wang

Ting-Ting Kuo

Chun-Huai Li

Chun-Yen Tseng

Kiyohiro Kawasaki

Jun He

Chih-Kang Wu

Chien-Chen Li

Chih-Ta Wu

Ching-Kun Lai

Tsung-Hsi Yang

Chih-Pin Huang

Ming-Chun Hsu

Ching-Yu Chou

Kuang-Fu Chang

Chih-Wei Tu

Chia-Hsun Tseng

Chih-Kai Hu

Li-Ping Huang

Chen-Hsing Cheng

Sung-Bin Lin

Fang-Cheng Lin

Ren-Wei Huang

Nai-Chen Peng

Ying-Xing Lee

Tien-I Wu

Shu-Wen Shen

Chi-Jer Wang

Ming-Kuan Kao

Hui-Chang Yu

Kuang-Pi Lee

Chih-Hung Li

Chien-Wei Huang

Hong-Jye Hong

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are shifted to align and connect to the power rail and the ground rail of the other one of the standard cells.

Integrated circuit layout including standard cells and method to form the same

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

Integrated circuit, method for forming a layout of integrated circuit using standard cells

The invention provides a semiconductor structure, which comprises a first standard cell and a second standard cell located on a substrate, wherein an isolation region is included between the first standard cell and the second standard cell, a plurality of fin structures and a plurality of gates form a plurality of transistors, which are respectively located in the first standard cell and the second standard cell, and a plurality of single diffusion breaks (SDBs) located in the first standard cell and the second standard cell. A plurality of first dummy grooves in the first standard cell and the second standard cell, and a plurality of second dummy grooves in the isolation region, wherein some of the second dummy grooves overlap the first dummy grooves.

Semiconductor structure and manufacturing method thereof

A static random access memory (SRAM) includes a substrate having a first active region and a second active region adjacent to the first active region. A first gate structure is disposed on the substrate and across the first active region and the second active region. A second gate structure is adjacent to a first side of the first gate structure. A first lower contact structure is disposed on the first active region and adjacent to a second side of the first gate structure. A first upper contact structure is disposed on and in direct contact with the first lower contact structure. A top surface of the first lower contact structure and a sidewall of the first upper contact structure comprise a step profile therebetween.

Static random access memory

Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

Heat dissipating features for laser drilling process

In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Fin field-effect transistor device and method of forming the same

The present disclosure provides a method of making a semiconductor device. The method includes forming a semiconductor stack on a substrate, wherein the semiconductor stack includes first semiconductor layers of a first semiconductor material and second semiconductor layers of a second semiconductor material alternatively stacked on the substrate; patterning the semiconductor stack and the substrate to form a trench and an active region being adjacent the trench; epitaxially growing a liner of the first semiconductor material on sidewalls of the trench and sidewalls of the active region; forming an isolation feature in the trench; performing a rapid thermal nitridation process, thereby converting the liner into a silicon nitride layer; and forming a cladding layer of the second semiconductor material over the silicon nitride layer.

Multigate device structure with engineered cladding and method making the same

In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

Methods for increasing germanium concentration of surfaces of a silicon germanium portion of a Fin and resulting semiconductor devices

An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface. The second semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the second semiconductor device has a second bottom surface, a second top surface and a second side surface connecting with the second bottom surface and the second top surface, the second side surface faces toward to the first side surface, the second side surface comprises a third sub-surface and a fourth sub-surface connected with each other, the third sub-surface is connected with the second bottom surface, and a second obtuse angle is between the third sub-surface and the fourth sub-surface. The underfill layer is between the first semiconductor device and the second semiconductor device, between the first semiconductor device and the redistribution structure, and between the second semiconductor device and the redistribution structure. The encapsulant encapsulates the first semiconductor device, the second semiconductor device and the underfill layer.

Semiconductor package and method of forming the same

The present invention provides a layout pattern of static random access memory, comprising a PU(first pull-up transistor), a PU(second pull-up transistor), a PDA (first pull-down transistor), a PDB (second pull-down transistor), a PDA (third pull-down transistor), a PDB (fourth pull-down transistor), a PGA (first access transistor), a PGB (second access transistor), a PGA (third access transistor) and a PGB (fourth access transistor) located on the substrate. The PDA and the PDB are connected in parallel with each other, the PDA and the PDB are connected in parallel with each other, wherein the gate structures include a first J-shaped gate structure, and the first J-shaped gate structure is an integrally formed structure.

Layout pattern of static random access memory

A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Encircling a semiconductor device with stacked frames on a substrate

When programming an MLC memory device, the disturb characteristics of a program block having multiple memory cells are measured, and the threshold voltage variations of the multiple memory cells are then acquired based on the disturb characteristics of the program block. Next, multiple initial program voltage pulses are provided according to a predetermined signal level, and multiple compensated program voltage pulses are provided by adjusting the multiple initial program voltage pulses. Last, the multiple compensated program voltage pulses are outputted to the program block for programming the multiple memory cells to the predetermined signal level.

Method of programming MLC memory device and related MLC memory device

A package structure is provided. The package structure includes a substrate and a chip-containing structure bonded to the substrate. The package structure also includes a warpage-control element attached to the substrate. The warpage-control element has a protruding portion extending into the substrate.

Package structure with warpage-control element

A semiconductor package includes a substrate, a semiconductor die, a ring structure and a lid. The semiconductor die is disposed on the substrate. The ring structure is disposed on the substrate and surrounds the semiconductor die, where a first side of the semiconductor die is distant from an inner sidewall of the ring structure by a first gap, and a second side of the semiconductor die is distant from the inner sidewall of the ring structure by a second gap. The first side is opposite to the second side, and the first gap is less than the second gap. The lid is disposed on the ring structure and has a recess formed therein, and the recess overlaps with the first gap in a stacking direction of the ring structure and the lid.

Semiconductor package and method of manufacturing the same

An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

Integrated circuit layout including standard cells of different gate line widths and same gate line pitch

Growing community of inventors

Hsinchu, Taiwan

Chien-Hung Chen