Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Hsueh Shih

Minghsing Tsai

Ming-Hsing Tsai

Hung-Wen Su

Shau-Lin Shue

Ting-Chu Ko

Chen-Hua Douglas Yu

Ming-Shih Yeh

Chen Hua Yu

Yung-Cheng Lu

Chung-Chi Ko

Hui-Lin Chang

Shih-Wei Chou

Pi-Tsung Chen

Shaulin Shue

A method and system is provided for efficiently varying the composition of the metal interconnects for a semiconductor device. A metal interconnect according to the present disclosure has an intermediate layer on a dielectric material, the intermediate layer having a relatively higher concentration of an impurity metal along with a primary metal, the impurity metal having a lower reduction potential than the primary metal. The metal interconnect has a main layer of the metal alloy interconnect on top of the intermediate layer and surrounded by the intermediate layer, the main layer having a relatively higher concentration of the primary metal than the intermediate layer, wherein the intermediate and main layers of the metal alloy interconnect each maintains a material uniformity.

Low resistance and reliable copper interconnects by variable doping

An integrated circuit includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a first opening in the low-k dielectric layer, and a first diffusion barrier layer in the first opening covering the low-k dielectric layer in the first opening, wherein the first diffusion barrier layer has a bottom portion connected to sidewall portions, and wherein the sidewall portions have top surfaces close to a top surface of the low-k dielectric layer. The integrated circuit further includes a conductive line filling the first opening wherein the conductive line has a top surface lower than the top surfaces of the sidewall portions of the diffusion barrier layer, and a metal cap on the conductive line and only within a region directly over the conductive line.

Process for improving copper line cap formation

An integrated circuit structure and methods for forming the same are provided. The integrated circuit structure includes a semiconductor substrate; a dielectric layer over the semiconductor substrate; an opening in the dielectric layer; a conductive line in the opening; a metal alloy layer overlying the conductive line; a first metal silicide layer overlying the metal alloy layer; and a second metal silicide layer different from the first metal silicide layer on the first metal silicide layer. The metal alloy layer and the first and the second metal silicide layers are substantially vertically aligned to the conductive line.

Transitional interface between metal and dielectric in interconnect structures

A chemical solution for an electro chemical plating process includes an electro chemical plating solution; and an additive, added in the electro chemical plating solution, substantially consisting of a polymer with one or more kinds of impurities, wherein each kind of the impurities has a density, with respect to the polymer, lower then 10atoms/cc.

Electro chemical plating additives for improving stress and leveling effect

An exemplary method includes: providing a substrate with exposed metal and dielectric surfaces, performing a reducing process on the metal and dielectric surfaces, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for selective metal layer deposition.

Process for low resistance metal cap

A conductive polymer between two metallic layers acts a glue layer, a barrier layer or an activation seed layer. The conductive polymer layer is employed to encapsulate a copper interconnection structure to prevent copper diffusion into any overlying layers and improve adhesive characteristics between the copper and any overlying layers.

Copper interconnection with conductive polymer layer and method of forming the same

Apparatus and method for metal electroplating. The apparatus for metal electroplating includes an electroplating tank for containing an electrolyte at a first temperature, a substrate holder for holding a semiconductor substrate, and a heater for heating the portion of the electrolyte adjacent to the substrate holder to a second temperature higher than the first temperature.

Method and apparatus for electroplating

An exemplary method includes: providing a substrate with an exposed metal surface, performing a reducing process on the metal surface, and transferring the substrate in an inert or reducing ambient to a chamber for that is used for metal layer deposition.

Process for making a metal seed layer

The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.

Uniform passivation method for conductive features

A method of forming a semiconductor device comprising: forming a gate dielectric layer over a channel region; forming a gate electrode on the gate dielectric layer; forming source/drain regions substantially aligned with respective edges of the gate electrode with the channel region therebetween; forming a thin metal layer on the source/drain regions; forming a metal alloy layer on the thin metal layer; and transforming the thin metal layer into a low resistance metal silicide.

Silicide structure for ultra-shallow junction for MOS devices

Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M, wherein Mis selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

Semiconductor device and fabrication method thereof

Electrochemical plating polymer additives and method which reduces metal overburden in an electroplated metal while optimizing gap fill capability are disclosed. The polymer additives are provided in an electrochemical plating bath solution and may include low cationic charge density co-polymers having aromatic and amine functional group monomers. The low cationic charge density polymers may include benzene or pyrollidone functional group monomers and imidazole or imidazole derivative functional group monomers.

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Taipei, Taiwan

Chien-Hsueh Shih