Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-Hsuan Liu

Hsin-Chi Chen

Jen-Pan Wang

Chih-Ming Lee

Chiang-Ming Chuang

Hung-Che Liao

Kun-Tsang Chuang

Chia-Ming Pan

Chao-Chi Chen

Ching-Hsien Chen

Kun-tsang Chuang

A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

Semiconductor device having non-continuous wall structure surrounding a stacked gate structure including a conductive layer disposed between segmented portions of the wall structure

A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring.

Vertical conductive structure surrounded by guard ring and method of making

A semiconductor device is provided. The semiconductor device includes a substrate, a stacked gate structure, and a wall structure. The stacked gate structure is on the substrate and extending along a first direction. The wall structure is on the substrate and laterally aside the stacked gate structure. The wall structure extends along the first direction and a second direction perpendicular to the first direction. The stacked gate structure is overlapped with the wall structure in the first direction and the second direction.

Semiconductor device having a wall structure surrounding a stacked gate structure

Semiconductor arrangement and method of making

A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, at least one memory cell, and at least one word line. The raised dummy feature is present on the semiconductor substrate and defines a cell region on the semiconductor substrate. The memory cell is present on the cell region. The word line is present adjacent to the memory cell.

Semiconductor structure and method for forming the same

A method of manufacturing a non-volatile memory is described. A substrate including a first region and a second region located at periphery of the first region is provided. A plurality of stacked structures are formed on the first region of the substrate. A wall structure is formed on the second region of the substrate. A conductive layer is formed over the substrate. A bottom anti-reflective coating is formed over the conductive layer. The bottom anti-reflective coating and the conductive layer are etched back. The conductive layer is patterned.

Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same

Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

Device manufacture and packaging method thereof

Various non-planar reflective lithography masks, systems using such lithography masks, and methods are disclosed. An embodiment is a lithography mask comprising a transparent substrate, a reflective material, and a reticle pattern. The transparent substrate comprises a curved surface. The reflective material adjoins the curved surface of the transparent substrate, and an interface between the reflective material and the transparent substrate is a reflective surface. The reticle pattern is on a second surface of the transparent substrate. A reflectivity of the reticle pattern is less than a reflectivity of the reflective material. Methods for forming similar lithography masks and for using similar lithography masks are disclosed.

Reflective lithography masks and systems and methods

A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.

Focus control apparatus for photolithography

Embodiments of mechanisms for forming a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate having a first device region and a second device region. The semiconductor device structure further includes first devices in the first device region and second devices in the second device region. The semiconductor device structure also includes a first annular structure continuously surrounding the first device region and a second annular structure continuously surrounding the second device region. The first annular structure has a first thermal diffusion coefficient less than a second thermal diffusion coefficient of the second annular structure.

Growing community of inventors

Tainan, Taiwan

Chien-Hsuan Liu