Other

Koninklijke Philips Corporation N.v.

Nxp B.v.

Trident Microsystems (far East) Ltd.

Chien-Hsin Lin

Shaori Guo

Selliah Rathnam

Gwo Giun Lee

Kevin Chin

Chang-Ming Yang

A pixel-data processing circuit delivers a fixed number of pixels to a video processing stage using an irregular sampling pattern that is defined by a variably-definable sampling window. In one example embodiment directed to processing an input stream of pixels corresponding to an array of video pixels, the window size is selected from one of various options for sampling subsets of the array as a two-dimensional window that spans the pixels in the array. A sampling-window is used such that the window size is a multiple of the sampling-window size and the sampling-window size defines the fixed number of pixels. The processing includes concurrently moving pixel data from the input stream into a first set of line buffers with the pixels stored in the first set of line buffers including pixels for the established window size, prefetching the stored pixels from the first set of line buffers into a second set of line buffers, the second set of line buffers being sufficiently long to store at least the pixels corresponding to the established sampling-window size, and fetching the fixed number of pixels from the second set of line buffers. In various applications, in addition to flexibility, the present invention realizes enhanced throughput.

Pixel-data line buffer approach having variable sampling patterns

Artifact detection and counting is enhanced using looping in both the horizontal and vertical direction is enhanced via a reduced bandwidth for accumulation of count values into count table entries. According to an example embodiment of the present invention, first and second loops are made for horizontal and vertical count table entries. Quotient and remainder values of a detected artifact value are used for increasing count table entries in the first looping pass, and the count table entries are increased using the quotient value in the second loop. The table increase in the first loop is limited to the length of the remainder value, and the table increase in the second loop is limited to the length of the row or column in the count table being used. In this manner, latency for additions to the count table and the bandwidth for making the additions are reduced, relative to conventional applications. In addition, each entry into the table can be reduced to one addition.

Video artifact identification and counting

According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2&#xd7;2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2&#xd7;2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Motion compensation with subblock scanning

A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle. Using a control circuit, the pixel-data processing circuit can switch between the first operational resizing mode and the second operational nonresizing mode.

Line-buffer reuse in vertical pixel-processing arrangement

The present invention is a cast-in-place foundation resist pile with substantially lateral extensions inexpensively formed before or after the cement has been poured into the pile hole excavation. In addition, the present invention preferably makes those lateral extensions of the foundation pile into at least one of the levels of soft soil where the pile hole excavation has been made in alternating levels or zones of relatively soft and hard soils.

Growing community of inventors

Sunnyvale, CA, United States of America

Chien-Hsin Lin