Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Globalfoundries U.S. Inc.

Chien-Hsin Lee

Mahadeva Iyer Natarajan

Manjunatha Govinda Prabhu

Xiangxiang Lu

Wei Gao

Haojun Zhang

Shaoqiang Zhang

Handoko Linewih

Anil Kumar

Tsung-Che Tsai

Vaddagere Nagaraju Vasantha Kumar

Wee Hua Tang

Manjunatha Prahbu

Krishna M Chavali

Ruchil Kumar Jain

A fin field effect transistor (FinFET) ESD device is disclosed. The device may include: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region over the substrate; an n-well region laterally abutting the p-well region over the substrate; a first P+ doped region over the p-well region; a first N+ doped region over the p-well region; and a second N+ doped region over the p-well region; and a Schottky diode electrically coupled to the n-well region, wherein the Schottky diode spans the n-well region and the p-well region, and wherein the Schottky diode controls electrostatic discharge (ESD) between the second N+ doped region and the n-well region.

FinFET ESD device with Schottky diode

The present disclosure generally relates to semiconductor structures and, more particularly, to transistor structures and methods of manufacture. The structure includes active metal lines separated by electrically floating metal layers which have a width less than a width of the active metal lines.

Transistor structures having electrically floating metal layers between active metal lines

Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET) comprising a gate, a source, and a drain, all extending parallel to each other in a first direction; at least one source electrostatic discharge (ESD) protection circuit; a source terminal disposed above and in electrical contact with the at least one source ESD protection circuit, wherein the source terminal extends in the first direction; at least one drain ESD protection circuit; and a drain terminal disposed above and in electrical contact with the at least one drain ESD protection circuit, wherein the drain terminal extends in the first direction.

Methods, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic discharge (ESD) protection

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Silicon controlled rectifier (SCR) based ESD protection device

High-voltage semiconductor devices with electrostatic discharge (ESD) protection and methods of fabrication are provided. The semiconductor devices include a plurality of transistors on a substrate patterned with one or more common gates extending across a portion of the substrate, and a plurality of first S/D contacts and a plurality of second S/D contacts associated with the common gate(s). The second S/D contacts are disposed over a plurality of carrier-doped regions within the substrate. One or more floating nodes are disposed above the substrate and, at least in part, between second S/D contacts to facilitate defining the plurality of carrier-doped regions within the substrate. For instance, the carrier-doped regions may be defined from a mask with a common carrier-region opening, with the floating node(s) intersecting the common carrier-region opening and facilitating defining, along with the common opening, the plurality of separate carrier-doped regions.

Transistors patterned with electrostatic discharge protection and methods of fabrication

E-fuse cells and methods for protecting e-fuses are provided. An exemplary e-fuse cell includes an e-fuse having a first end coupled to a source node and a second end selectively coupled to a ground. Further, the exemplary e-fuse includes a selectively activated shunt path from the source node to the ground. Also, the exemplary e-fuse includes a device for activating the shunt path in response to an electrical overstress event.

E-fuse cells

The SCR-based ESD device has a 4-layered PNPN structure (NPN and PNP junction transistors) disposed in SOI having first and second device wells (N-well and P-well) abut forming a NP junction near a midline. First and second contact regions disposed in device wells are coupled to high and low power sources (I/O pad and ground). Internal isolation regions (shallower STI) extending partially not touching the bottom of surface substrate separate the first and second contact regions. A vertical gate is disposed over the NP junction or over a shallower STI which overlaps the NP junction and separate the second contact regions in x-direction. One or more horizontal gates separate the second contact regions in y-direction and guide the device wells underneath the shallower STI to outer edges to connect with the first contact regions for body contacts. A process for forming the device is also disclosed and is compatible with CMOS processes.

Transistor structures having electrically floating metal layer between active metal lines

Structures for a frequency divider, methods of fabricating a frequency divider, and method of using a frequency divider. A first interconnect line is configured to selectively conduct a first signal of a first frequency. A second interconnect line is coupled with the first interconnect line. The second interconnect line is configured to selectively conduct a second signal of a second frequency. The first frequency is less the second frequency.

Electrostatic discharge protection device and methods

Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a p-type substrate; a silicon-controlled rectifier (SCR) over the p-type substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode including a gate in the n-well region, the Schottky diode positioned to mitigate electrostatic discharge (ESD) across the negatively charged fin and the n-well region in response to application of a forward voltage across the gate.

Diode-triggered Schottky silicon-controlled rectifier for Fin-FET electrostatic discharge control

Methods form integrated circuit structures that include a device layer having electronic devices on a substrate, and a multi-layer interconnect structure connected to the device layer. The multi-layer interconnect structure includes alternating insulator layers and wiring layers, power and ground wiring in the wiring layers, non-functional wiring in the wiring layers called dummy fill, and conductive vias extending through the insulator layers. The conductive vias connect the power and ground wiring in the wiring layers to the electronic devices in the device layer. The non-functional wiring is insulated from the power wiring in the wiring layer, and from the electronic devices in the device layer. The conductive vias connect the non-functional wiring (the dummy fill) in the wiring layers through the substrate, or a ground bus, thereby continuously removing static charge that would otherwise accumulate during manufacturing processes.

Dissipation of static charge from wiring layers during manufacturing

Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

Methods for an ESD protection circuit including trigger-voltage tunable cascode transistors

Method, apparatus, and system for metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic discharge (ESD) protection

Various embodiments include fin-type field effect transistor (FinFET) structures. In some cases, a FinFET structure includes: a substrate; a silicon-controlled rectifier (SCR) over the substrate, the SCR including: a p-well region and an adjacent n-well region over the substrate; and a negatively charged fin over the p-well region; and a Schottky diode electrically coupled with the SCR, the Schottky diode spanning between the p-well region and the n-well region, the Schottky diode for controlling electrostatic discharge (ESD) across the negatively charged fin and the n-well region.

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Malta, NY, United States of America

Chien-Hsin Lee