Broadcom Corporation

Chien-Hsien Wu

Bruce Hui Kwan

Weihuang Wang

Philip H Chen

Karagada Ramarao Kishore

Vamsi M Tatapudi

Mohan V Kalkunte

Mohammad Kamel Issa

Michael Lau

Venkateshwar Buduma

Eugene Opsasnick

Song-Huo Yu

Weitong Chuang

Maya Suresh

Anupam Anand

K R Kishore

Samir Kishore Sanghani

Yook-Khai Cheok

Robert (Yi) Li

Morris Beatty

A multi-ported memory that supports multiple read and write accesses is described. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for read operation(s) and write operation(s) to be received during the same clock cycle. In the event that an incoming write operation is blocked by read operation(s), data for that write operation may be stored in one of a plurality of cache banks included in the multi-port memory. The cache banks are accessible to both write and read operations. In the event than the write operation is not blocked by read operation(s), a determination is made as to whether data for that incoming write operation is stored in the memory bank targeted by that incoming write operation or in one of the cache banks.

Multi-ported memory with multiple access support

A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Memory device with a logical-to-physical bank mapping cache

A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Disclosed are various embodiments that provide serial replication of multicast packets by performing a first data fetch to fetch first data from a memory buffer, the first data comprising a first packet pointer representing a first packet and a replication number indication a number of times the first packet is to be replicated. Furthermore, various embodiments are directed to performing a second data fetch to fetch second data from a memory buffer, the second data comprising a first packet pointer representing a second packet and serially replicating the first packet and the second packet based at least in part upon the replication number and a predetermined threshold value.

Serial replication of multicast packets

A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data and at least one egress module for transmitting the incoming data to at least one egress port. The at least one egress module includes an egress scheduling module and multiple queues per each of the at least one egress port. Each of the multiple queues serve data attributable to a class of service, and the egress scheduling module is configured to service a minimum bandwidth requirement for each of the multiple queues and then to service the multiple queues to allow for transmission of a maximum allowable bandwidth through a weighting of each of the multiple queues.

Scheduling of data transmission with minimum and maximum shaping of flows in a network device

The present invention is directed to a network device, method and apparatus for processing data. The present invention includes at least one ingress module for performing switching functions on incoming data. The invention further includes a memory management unit (MMU) for storing the incoming data, and at least one egress module for transmitting the incoming data to at least one egress port. Further, in the present invention, the memory management unit further comprises a cell copy count pool (CCP) memory, wherein the CCP determines when a memory cell can be made available.

Cell copy count

A network device for processing data includes at least one ingress module for performing switching functions on incoming data, a memory management unit for storing the incoming data in a memory and at least one egress module for transmitting the incoming data to at least one egress port. The memory management unit is configured to receive data at a clock speed for the network device and write the data to the memory using a multiplied clock speed that is a multiple of the clock speed for the network device, read out the data from the memory at the multiplied clock speed and provide the data to the at least one egress module at the clock speed for the network device, where the multiplied clock speed is used to sample the clock speed for the network device to place domains of the multiplied clock speed and the clock speed for the network device in phase.

Processing of multiple cells in a network device with two reads and two writes on one clock cycle

Methods, systems, and devices are provided for managing flow of datagram traffic, generally across networks. According to some of these methods, a flow control mechanism is used to avoid over-subscription of some ports without pausing extended areas of a network. According to other methods, a congestion control mechanism is used to minimize datagram traffic between a port sending datagrams to an over-subscribed port and the over-subscribed port itself.

Flow control and congestion control in a data distribution network

A network device for scheduling packets in a plurality of queues includes a plurality of leaky bucket modules, each of the plurality of leaky bucket mechanisms being associated with one of a plurality of queues and configured to process information based on a predefined bandwidth, a scheduler configured to schedule services of the plurality of queues and a metering module for tracking whether or not the plurality of queues has exceeded a predefined threshold through the leaky bucket modules. If the plurality of queues has exceeded the predefined threshold, the metering module is configured to compute a new bandwidth allocation for each of the plurality of queues, the new bandwidth allocation replacing the predefined bandwidth and being proportional to the predefined bandwidth for each of the plurality of queues.

Rate limiting and minimum and maximum shaping in a network device

Methods for aging datagrams in the memory portion of a datagram distribution device or other network device are provided. According to some of these methods, an attribute of each datagram entering the device may be used to assign an initial aging counter value to each datagram. Then, the attribute-specific aging counter values may be used to extend the time until expiration of certain datagrams relative to other datagrams. Also, devices for implementing these methods are provided.

Saturated datagram aging mechanism

Cell copy count hazard detection

A first set of instructions associated with an egress of a datagram may be determined, the first set of instructions identifying a first subset of a second set of instructions, the first subset including multiple individual network identifiers identifying which network portion to transmit a replication of the datagram. Which one of the multiple individual network identifiers corresponds to the datagram may be determined from the first subset of the second set of instructions and may be based on the egress of the datagram, wherein each network identifier corresponds to a different egress. The replication of the datagram may be provided to the egress of the determined network identifier for transmission to the network portion as identified by the determined network identifier corresponding to the datagram.

Compression of datagram distribution information

Aspects of a method and system for packet rate shaping may include an MMU that enables classification of one or more packets based on a CoS and/or an egress port, and transmission of the packets in accordance with a specified packet rate based on the classification.

Method and system for packet rate shaping

A network device for processing packets includes an ingress module for performing switching functions on an incoming packet, a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting a modified packet to an appropriate egress port. The egress module is configured to send an unmodified version of the incoming packet to an ingress mirrored-to-port when an ingress port, upon which the incoming packet is received, is configured to mirror packets received by the ingress port.

Mirroring of data in a network device

A network device for processing packets. The network device includes a memory management unit for storing packets and performing resource checks on each packet and an egress module for performing packet modification and transmitting the packet to a destination port. The memory management unit includes a timer for indicating that a free space should be created on a bus slot between the memory management unit and the egress module, wherein the free space is used for transmitting CPU instructions from the memory management unit to the egress module.

Growing community of inventors

Cupertino, CA, United States of America

Chien-Hsien Wu