Taiwan Semiconductor Manufacturing Comp. Ltd.

Askey Computer Corporation

Chien-Hao Huang

Katherine H Chiang

Chung-Te Lin

Cheng-Yi Wu

Gao-Ming Wu

Cheng-Lung Hung

Yun-Feng Kao

Keh-Chiang Ku

Ming-Yen Chuang

Yong-Tian Hou

Chien-Hao Chen

Li-Ting Wang

Ching-Feng Hsieh

Yu-Chang Lin

Li-Shyue Lai

Chia-Yu Ling

Chih-Wei Huang

Wenli Lin

Chih-Ming Yang

Chao-Nan Tsai

Chin-Ching Chang

Chun-Hsiung Tsai

Pi-Chi Chang

Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.

Transistor structure and method of forming the same

A disclosed capacitor structure includes a support structure including a plurality of elongated structures each extending along a longitudinal direction, a transverse direction, and a vertical direction. The plurality of elongated structures includes an alternating stack of first dielectric layers and second dielectric layers, a bottom electrode formed over the support structure, a third dielectric layer formed over the bottom electrode, and a top electrode formed over the third dielectric layer. Each of the first dielectric layers includes a first width along the transverse direction and each of the second dielectric layers includes a second width along the transverse direction. In various embodiments, the first width may be less than the second width such that each of the plurality of elongated structures include walls including a corrugated width profile as a function of distance along the vertical direction. The capacitor structure may be formed in a BEOL process.

Capacitor structure and method of making the same

A memory device includes an alternating stack of dielectric layers and word line layers, pairs of bit lines and source lines spaced apart from one another, a data storage layer covering a sidewall of the alternating stack, and channel layers interposed between the data storage layer and the pairs of bit lines and source lines. The alternating stack includes a staircase structure in a staircase-shaped region, and the staircase structure steps downward from a first direction and includes at least one turn. The pairs of bit lines and source lines extend in a second direction that is substantially perpendicular to the first direction and are in lateral contact with the data storage layer through the channel layers. A semiconductor structure and a method are also provided.

Memory device and method of forming the same

A three-dimensional integrated structure and the manufacturing method(s) thereof are described. The three-dimensional integrated structure includes a substrate having conductive features therein, and a component array disposed over the substrate and on the conductive features. The component array includes a metallic material layer and capacitor structures separated by the metallic material layer. Each of the capacitor structures includes a first metallic pillar, a first dielectric sheath surrounding the first metallic pillar, a second metallic sheath surrounding the first dielectric sheath, and a second dielectric sleeve surrounding the second metallic sheath. The metallic material layer laterally encapsulates the capacitor structures.

Three-dimensional integrated structure and manufacturing method thereof

A two-dimensional array of discrete dielectric template structures is formed over a substrate. A first dielectric spacer matrix may be formed in lower portions of the trenches between the discrete dielectric template structures. A second dielectric spacer matrix layer may be formed in upper portions of the trenches. A pair of a source cavity and a drain cavity may be formed within a volume of each of the discrete dielectric template structures. A source electrode and a drain electrode may be formed in each source cavity and each drain cavity, respectively. The gate electrodes may be formed prior to, or after, formation of the two-dimensional array of discrete dielectric template structures to provide a two-dimensional array of field effect transistors that may be connected to, or may contain, memory elements.

Self-aligned multilayer spacer matrix for high-density transistor arrays and methods for forming the same

A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature, and while the NVM array is heated to the target temperature, programming a subset of the NVM cells to first resistance levels and obtaining a first current distribution, programming the subset of NVM cells to second resistance levels and obtaining a second current distribution, calculating a current threshold level from the first and second current distributions, and for each of the NVM cells, programing the NVM cell to one of the first or second resistance levels, and using the current threshold level to determine a first pass/fail (P/F) status and a second P/F status at the programmed resistance level. A bit error rate (BER) of the NVM array is calculated based on the first and second current distributions and the first and second P/F status of each of the NVM cells.

Memory array test method and system

Semiconductor structures and methods of forming the same are provided. A semiconductor structure includes gate electrodes and first insulation patterns laterally disposed and alternately arranged on a substrate, a gate dielectric layer disposed on the gate electrodes and the first insulation patterns, at least one channel pattern disposed on the gate dielectric layer, source electrodes and drain electrodes laterally disposed and alternately arranged on the channel pattern, and second insulation patterns disposed on the channel pattern between the source and drain electrodes. Besides, from a top view, each of the drain electrodes is overlapped with one of the first insulation patterns.

Semiconductor structures and methods of forming the same

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is checked, using machine learning, whether the at least one fail bit is unrepairable, according to the location of the at least one fail bit, and the available repair resource. When the checking indicates that the at least one fail bit is not unrepairable, it is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected.

Method, system and computer program product for memory repair

A semiconductor die includes a semiconductor substrate and a transistor array disposed over the semiconductor substrate. The transistor array includes unit cells and spacers. The unit cells are disposed along rows of the transistor array extending in a first direction and columns of the transistor array extending in a second direction perpendicular to the first direction. The spacers encircle the unit cells. The unit cells include source contacts and drain contacts separated by interlayer dielectric material portions. First sections of the spacers contacting the interlayer dielectric material portions are thicker than second sections of the spacers contacting the source contacts and the drain contacts.

Semiconductor device and manufacturing method thereof

A semiconductor device is provided, which contains a memory bank including M primary word lines and R replacement word lines, a row/column decoder, and an array of redundancy fuse elements. A sorted primary failed bit count list is generated in a descending order for the bit fail counts per word line. A sorted replacement failed bit count list is generated in an ascending order of the M primary word lines in an ascending order. The primary word lines are replaced with the replacement word lines from top to bottom on the lists until a primary failed bit count equals a replacement failed bit count or until all of the replacement word lines are used up. Optionally, the sorted primary failed bit count list may be re-sorted in an ascending or descending order of the word line address prior to the replacement process.

Memory repair using optimized redundancy utilization

A method of testing a non-volatile memory (NVM) array includes obtaining a current distribution of a subset of NVM cells of the NVM array, the current distribution including first and second portions corresponding to respective logically high and low states of the subset of NVM cells, programming an entirety of the NVM cells of the NVM array to one of the logically high or low states, determining an initial bit error rate (BER) by performing first and second pass/fail (P/F) tests on each NVM cell of the NVM array, and using the current distribution to adjust the initial BER rate. Each of obtaining the current distribution, programming the entirety of the NVM cells, and performing the first and second P/F tests is performed while the NVM array is heated to a target temperature.

Provided are a semiconductor device and method of forming the same. The semiconductor device includes active components and a first barrier pattern. The active components are on a substrate. Each of the active components includes base insulation patterns on the substrate, gate electrodes on the substrate and spaced apart from each other with the base insulation patterns interposed therebetween, a gate dielectric layer on the gate electrodes and the base insulation patterns, a channel pattern on the gate dielectric layer, source electrodes on the channel pattern and spaced apart from each other, a drain electrode on the channel pattern and between the source electrodes, and second insulation patterns between the source electrodes and the drain electrode. The first barrier pattern disposed on the gate dielectric layer surrounds the channel patterns, the source electrodes, the drain electrodes, and the second insulation patterns of each of the active components.

Semiconductor device including an active component and a barrier pattern surrounding the active component and method of forming the same

A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.

A location of at least one fail bit to be repaired in a memory block of a memory is extracted from at least one memory test on the memory block. An available repair resource in the memory for repairing the memory block is obtained. It is determined whether a Constraint Satisfaction Problem (CSP) containing a plurality of constraints is solvable. The constraints correspond to the location of the at least one fail bit in the memory block, and the available repair resource. In response to determining that the CSP is not solvable, the memory block is marked as unrepairable or the memory is rejected. In response to determining that the CSP is solvable and has a solution satisfying the constraints, the at least one fail bit is repaired using the available repair resource in accordance with the solution of the CSP.

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Banciao, Taiwan

Chien-Hao Huang