Tsinghua University

Chien-Fu Chen

Meng-Fan Chang

Hiroyuki Yamauchi

Chien-Chen Lin

Ting-Hao Chang

Yen-Yao Wang

A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first NMOS transistor, and a second NMOS transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first NMOS transistor has a gate terminal coupled to a first word line. The first NMOS transistor has a source terminal coupled to the first node. The second NMOS transistor has a gate terminal coupled to a second word line, and the second NMOS transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first NMOS transistor, and the second high supply voltage provides a first boost voltage simultaneously.

6T static random access memory cell, array and memory thereof

A ternary content-addressable memory comprises a first switch, a first static random-access memory cell, a second switch and a second static random-access memory cell. The first switch is connected between a first search line and a match line. The first switch has a first control electrode. The first static random-access memory cell has a first storage node connected to the first control electrode of the first switch. The second switch is connected between a second search line and the match line. The second switch has a second control node. The second static random-access memory cell has a second storage node connected to the second control electrode of the second switch.

Ternary content-addressable memory

A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. A first high supply voltage and a low supply voltage are coupled to the first inverter. A second high supply voltage and the low supply voltage are coupled to the second inverter. The first access transistor has a gate terminal coupled to a first word line. The first access transistor has a source terminal coupled to the first node. The second access transistor has a gate terminal coupled to a second word line, and the second access transistor has a source terminal coupled to the second node. The first word line provides ON signals to turn on the first access transistor, and the second high supply voltage provides a first differential voltage simultaneously.

A 6T static random access memory cell, array, and memory thereof are provided, in which the memory cell includes a first inverter, a second inverter, a first access transistor, and a second access transistor. The first inverter and second inverter respectively include a first pull-up transistor, a first pull-down transistor, a second pull-up transistor and a second pull-down transistor. The first pull-down and pull-up transistors each have a drain terminal mutually coupled to form a first node. The second pull-down and pull-up transistors each have a drain terminal mutually coupled to form a second node. The first and second access transistors each have a gate terminal respectively coupled to a first word line and a second word line. When the first word line provides on signals to turn on the first access transistor, the second low voltage supply provides a first differential voltage simultaneously.

Growing community of inventors

Hsinchu, Taiwan

Chien-Fu Chen