Industrial Technology Research Institute

United Microelectronics Corp.

National Yang Ming Chiao Tung University

Macroblock, Inc.

Chien-Chung Lin

Chih-Hung Chen

Kuo-Ju Chen

Ming-Hsien Wu

Yen-Hsiang Fang

Chia-Hsin Chao

Hao-Chung Kuo

Ming-Jer Kao

Po-Hsun Wang

Cheng-Yu Hung

Chien-Mei Wang

Hau-Vei Han

Feng-Pin Chang

A display device including a circuit substrate, a plurality of pixels, and a light-shielding layer is provided. The pixels include a plurality of light-emitting elements. The light-emitting elements are disposed on the circuit substrate and are electrically connected to the circuit substrate. The light-emitting elements in the pixels are arranged along an arrangement direction. The light-shielding layer is disposed on the circuit substrate and has a plurality of pixel apertures. The pixels are disposed in a corresponding pixel aperture. The light-shielding layer includes a plurality of first light-shielding patterns extending in the arrangement direction and a plurality of second light-shielding patterns connected to the first light-shielding patterns. The extending direction of the second light-shielding patterns is different from the extending direction of the first light-shielding patterns. A thickness of the first light-shielding patterns is greater than or substantially equal to a thickness of the second light-shielding patterns.

Display device

An optical sheet is disclosed in the present invention and comprises a substrate, a reflective layer and a plurality of pixels. The reflective layer is disposed on the substrate. The pixels are composed of several quantum dot fluorescent powders respectively and arrayed on the reflective layer. In addition, a method for manufacturing the above optical sheet, a light emitting diodes module and a display using the above optical sheet are also disclosed in the present invention.

Optical sheet, method for manufacturing the same, light emitting diodes module and display using the same

A metal interconnect structure generally includes a lower-layer metal wiring, an upper-layer metal wiring partially overlapping with the lower-layer metal wiring to define a via region thereof, a dielectric layer disposed between the lower-layer metal wiring and the upper-layer metal wiring, a plurality of via plugs arranged in the dielectric layer within a first area of the via region for electrically connecting the lower-layer metal wiring and the upper-layer metal wiring, and a plurality of first dielectric structures embedded in the upper-layer metal wiring within a second area of the via region, in which the first area does not overlap with the second area.

Metal interconnect structure

Growing community of inventors

Taipei, Taiwan

Chien-Chung Lin