United Microelectronics Corp.

Taiwan Semiconductor Manufacturing Comp. Ltd.

E Ink Holdings Inc.

Au Optronics Corporation

Ccilu International Inc.

Tunghai University

Taichung Veterans General Hospital

Chien-Chung Huang

Teng-Chun Tsai

Neng-Kuo Chen

Yi-Wei Chen

Nien-Ting Ho

Yu-Ru Yang

Jyu-Horng Shieh

Chih-Yuan Ting

Tai-Yen Peng

Kuo-Chih Lai

Yu-Shu Chen

Han-Ting Lin

Sin-Yi Yang

Chen-Jung Wang

Yeong-Chih Lai

Huang-Hui Wu

Yu-Tai Tsai

Wen-Han Hung

Hui-Hsien Wei

Yu-Ping Wang

Chien-Ming Lai

Su-Jen Sung

Ya-Huei Tsai

Mei-Ling Chen

Yu-Ting Tseng

Shao-Ta Hsu

Yen-Chu Chen

Keng-Jen Liu

Shyh-Fann Ting

Chin-Fu Lin

Cheng-Tung Huang

Yu-Tsung Lai

Tzyy-Ming Cheng

Kun-Hsien Lee

Wen-Chang Kuo

Li-Shian Jeng

Tsai-Fu Chen

Chin-Wen Lin

Shao-Chung Hu

Hua-Gang Chang

Yeng-Fong Shih

Yi-Lin Huang

Shen Hsiang Yin

Wei-Juin Chen

Ching-Kai Lo

Shu-Li Chang

Kok Seen Lew

En-Chiuan Liou

Ssu-I Fu

Chi-Mao Hsu

Chih-Wei Yang

Yi-Wen Chen

Chang-Sheng Lin

Chao-Ching Hsieh

Chia-Fu Hsu

Jei-Ming Chen

Tsai-Fu Hsiao

Tzung-Yu Hung

Jian-Cun Ke

Tsung-Yin Hsieh

Hung-Yi Wu

Su-Cheng Liu

Huei-Wen Yang

Yu-Feng Huang

Yu-Feng Liu

Ya-Ling Chen

Chui-Chung Chiu

Kai-Chih Pai

Lun-Chi Chen

Ruey-Kai Sheu

Yan-Nan Lin

Ta-Chun Hung

Chien-Lun Liao

Chieh-Liang Wu

Min-Shian Wang

Man-Wen Shih

Tien-Der Chiang

Chun Yi Chen

Dan-Ru Wang

Chao-Lon Yang

Hsiao-Lung Chu

Huai-Tze Yang

Chun-Ming Lai

Chia-Tien Hsu

Shang-Feng Tsai

Tsai-Jung Wang

Cheng-Hsu Chen

Chun-Te Huang

Szu-Chin Chen

Hui-Chun Kuo

An integrated circuit includes a metallization pattern having first and second conductive features, an etch stop layer over the metallization pattern, a memory device, a bottom electrode via, a third conductive feature, and a dielectric feature. The etch stop layer has first and second portions over the first and second conductive features, respectively. The bottom electrode via is in the first portion of the etch stop layer and electrically connecting the memory device over the first portion of the etch stop layer to the first conductive feature. The third conductive feature is in the second portion of the etch stop layer and electrically connected to the second conductive feature. The dielectric feature is between the first and second portions of the etch stop layer and in contact with sidewalls of the first and second portions of the etch stop layer.

Integrated circuit

An acute kidney injury predicting system and a method thereof are proposed. A processor reads the data to be tested, the detection data, the machine learning algorithm and the risk probability comparison table from a main memory. The processor trains the detection data according to the machine learning algorithm to generate an acute kidney injury prediction model, and inputs the data to be tested into the acute kidney injury prediction model to generate an acute kidney injury characteristic risk probability and a data sequence table. The data sequence table lists the data to be tested in sequence according to a proportion of each of the data to be tested in the acute kidney injury characteristics. The processor selects one of the medical treatment data from the risk probability comparison table according to the acute kidney injury characteristic risk probability.

Acute kidney injury predicting system and method thereof

An integrated circuit includes a dielectric layer, a memory device, and a resistor. The memory device includes a bottom electrode via, a bottom electrode, a resistance switching element, and a top electrode. The bottom electrode via is in the dielectric layer. The dielectric layer has a first portion extending along sidewalls of the bottom electrode via, a second portion extending laterally from the first portion, and a third portion. The bottom electrode is over the bottom electrode via. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The resistor is over the third portion of the dielectric layer. A thickness of the third portion of the dielectric layer is greater than a thickness of the second portion of the dielectric layer.

An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.

A method for manufacturing a shoe part includes: the first mixing step, the standing step, the second mixing step, the setting step, and the hot press forming step. The invention mainly uses the waste coffee grounds material as raw material to manufacture the shoe part. In addition to the aroma of coffee, the shoes have the functions of deodorization and dehumidification while being worn by the user, thereby achieving multiple objectives of environmentally friendly materials, low cost, strong structure and environmentally friendly after-use treatment.

Method for manufacturing a shoe part

The present invention provides a shoe material part mainly composed of a coffee ground material, a porous material and a rubber-plastic material, and is made of a recycled waste porous material and recycled waste coffee grounds, which can improve the value of waste recycling and reuse, and reduce environmental pollution, in addition to reducing waste, there will be no residue pollution of natural ecology and other issues in the subsequent environmental recycling, quite in line with environmental requirements. In addition, the present invention has the function of natural deodorization, because the coffee grounds can naturally diffuse the aroma of coffee, and the characteristics of better deodorization and air permeability of the coffee grounds can be used to reduce the foul smell of a user's foot.

Shoe material part

A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.

Integrated circuit and fabrication method thereof

A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.

Memory device and fabrication method thereof

The present disclosure provides a bottom electrode substrate for a segment-type electrophoretic display. The bottom electrode substrate includes a flexible substrate, a first conductive layer, an insulating layer, a second conductive layer and a segment-type electrode. The first conductive layer is disposed on the flexible substrate. The insulating layer covers the first conductive layer and the flexible substrate, wherein the insulating layer has at least one opening exposing a part of the first conductive layer. The second conductive layer is filled in the opening and in contact with the exposed first conductive layer. The segment-type electrode covers the second conductive layer and the insulating layer, and is in contact with the second conductive layer. A method for manufacturing the bottom electrode substrate is also provided herein.

Bottom electrode substrate for segment-type electro-phoretic display and method for manufacturing thereof

The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Method of forming complementary metal oxide semiconductor device with work function layer

A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.

Shift register

A mobile display system includes a first mobile display device and a second mobile display device. The first mobile display device includes a first power storage module, a first screen, and a wireless power transmitter. The first screen is configured to display a first image by using the power stored in the first power storage module. The second mobile display device includes a second power storage module, a second screen, and a wireless power receiver. The second screen is configured to display a second image by using the power stored in the second power storage module. During a period when the first power storage module is charged, the wireless power transmitter provides a first wireless power signal to the wireless power receiver, so as to charge the second power storage module by the first wireless power signal.

Mobile display system and mobile display device

A CMOS transistor and a method for manufacturing the same are disclosed. A semiconductor substrate having at least a PMOS transistor and an NMOS transistor is provided. The source/drain of the PMOS transistor comprises SiGe epitaxial layer. A carbon implantation process is performed to form a carbon-doped layer in the top portion of the source/drain of the PMOS transistor. A silicide layer is formed on the source/drain. A CESL is formed on the PMOS transistor and the NMOS transistor. The formation of the carbon-doped layer is capable of preventing Ge out-diffusion.

Method for manufacturing CMOS transistor

Complementary metal oxide semiconductor device

A method of manufacturing a semiconductor device includes forming an epitaxial layer within a source/drain region of a semiconductor substrate, forming a fluorine-containing layer on the surface of the epitaxial layer, forming a metal gate structure within the gate region after the step of forming the fluorine-containing layer, forming an interlayer dielectric to cover the semiconductor substrate, the epitaxial layer and the metal gate structure, forming a contact hole penetrating the interlayer dielectric to expose a portion of the epitaxial layer, forming a metal silicide layer on or in the epitaxial layer on a bottom of the contact hole so that the fluorine-containing layer is disposed on the periphery of the metal silicide layer.

Method of manufacturing a semiconductor device

Growing community of inventors

Taichung, Taiwan

Chien-Chung Huang