Powerchip Semiconductor Corporation

Mediatek Corporation

Richtek Technology Corporation

Powerchip Technology Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Winbond Electronics Corporation

Tsinghua University

Ricktek Technology Corporation

Chien-Chung Chen

Hung-En Tai

Sheng-Jen Wang

Hsing-Shen Huang

Chun-Yuan Hsu

Yung-Hsieh Lin

Yan-Jhih Huang

Yu-Wen Ho

Jyun-Da Wu

Shih-Tsung Hsiao

Wei-Jen Chen

Arnold Chang-Mou Yang

You-Min Yeh

Rei-Fu Huang

Siou-Shen Lin

Che-Yuan Jao

Shei-Chie Yang

Ching-Ly Yueh

Hung-Der Lin

Haw-Jyue Luo

Chia-Hsien Liu

Po-Tsun Chen

Hsing--Shen Huang

Li-Chin Wang

Ching-hsiang Liao

Hsan-Fong Lin

Huang-Wei Wu

Huang-Wen Chen

Sheng-Hsiu Peng

A method of making a semiconductor device includes forming a circuit layer over a substrate. The method further includes depositing an insulator over the substrate. The method further includes patterning the insulator to define a test line trench, a first trench, and a second trench, wherein the first trench is on a portion of the substrate exposed by the circuit layer. The method further includes filling the test line trench to define a test line electrically connected to the circuit layer. The method further includes filling the first trench and the second trench to define a capacitor.

Method of making semiconductor device including metal insulator metal capacitor

A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line electrically connected to the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer. The capacitor further includes an insulator surrounding the first conductor.

Semiconductor device including metal insulator metal capacitor and method of making

A display apparatus includes a timing controller and a gate-driver on array (GOA) control circuit. The timing controller generates a frame synchronization signal. The GOA control circuit is coupled to the timing controller and includes a scan signal management circuit and a level shifter. The scan signal management circuit generates a scan signal management signal according to the frame synchronization signal, a predetermined panel parameter, and an operation clock signal. The scan signal management circuit includes a storage unit which stores the predetermined panel parameter. The level shifter generates a scan control signal according to the scan signal management signal to control a GOA of a display panel circuit. The GOA generates a gate driving signal to control a vertical scan operation of the display panel circuit.

Display apparatus and gate-driver on array control circuit thereof

The present invention provides a display apparatus, including: a display panel circuit which includes a panel load line and performs a scanning display operation; and a panel driving circuit. The panel driving circuit determines at least a test phase and a scanning display phase according to a display control signal generated by a timing control circuit, wherein the test phase is a partial time period when the panel driving circuit does not perform the scanning display operation. The panel driving circuit generates a test driving signal on the panel load line, and detects an electronic characteristic of the display panel circuit so as to determine a failure item thereof during the test phase according to a pre-determined test instruction. The panel driving circuit generates a display driving signal on the panel load line for the scanning display operation according to the display control signal during the scanning display phase.

Display apparatus with testing functions and driving circuit and driving method thereof

A nonparametric method for measuring a clustered level of time rank in binary data is provided. A sample set of engineering data is classified into a target group and a reference group, and a rank is set to each sample in a chronological order. A minimum rank and a maximum rank are obtained from the target group, by which a characteristic period is defined. In the characteristic period, an average rank values of the target group and an average rank value of the reference group are calculated. After creating a dummy sample set, the dummy sample set is incorporated into an analysis data set and a new rank is set based on a comparison result of the average rank value of the target group and the average rank value of the reference group, and the minimum rank and the maximum rank of the characteristic period to obtain adjusted test data. A Mann-Whitney U test is executed on the adjusted test data to obtain a clustered level index of time rank in binary data.

Nonparametric method for measuring clustered level of time rank in binary data

A process control method is provided for performing a deposition process on a plurality of wafers of a batch. The process control method includes: deciding a placement location of the wafers of the batch according to the history information of a tool and the product information of the batch; calculating a target value of each placement location according to the placement location of the wafers of the batch and the history information of the tool; calculating a process parameter according to the history information of the tool, the product information of the batch, and the target value of each placement location; and performing a deposition process according to the placement location of the wafers of the batch and the process parameter.

Process control method and process control system

A dispatch control method for a furnace process including the following steps is provided. Before a plurality of lots of wafers is loaded into a furnace, the characteristic variation value of each of the plurality of lots of wafers is calculated. The plurality of lots of wafers is ordered according to the size of the characteristic variation values. The plurality of lots of wafers is placed in the furnace in a descending order of the characteristic variation values corresponding to a plurality of locations in the furnace causing the characteristic variation values to change from smaller to larger.

Dispatch control method for furnace process

The present invention provides a method for enhancing optoelectronic properties of polymers that contain conjugated moieties in their molecular structures (hereby denoted as 'conjugated polymers'), to be used in lighting, photovoltaics, other various optoelectronic devices and applications. The method of the present invention includes preparing a conjugated polymer layer or multiple conjugated polymer layers and imprinting the conjugated polymer layer or layers through the application of a mold or multiple molds.

Method for enhancing optoelectronic properties of conjugated polymers

An electrically programmable fuse (e-fuse) apparatus includes an e-fuse macro and a switch device. The e-fuse macro is disposed in an integrated circuit, and has a plurality of e-fuse units. The switch device is disposed in the integrated circuit, and has an output node coupled to the e-fuse units and a first input node coupled to a first power source which supplies a first reference voltage acting as a programming voltage of the e-fuse macro. The switch device connects the first power source to the e-fuse units when the e-fuse macro is operated under a programming mode.

E-fuse apparatus for controlling reference voltage required for programming/reading e-fuse macro in an integrated circuit via switch device in the same integrated circuit

Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal.

Integrated circuit with power control and power control method thereof

A driving system and method for electroluminescent displays which by connecting the electroluminescent elements that have been lighted up to the electroluminescent elements that are to be lighted up causes charge to be shared among the elements, so as to increase the voltage level at the anodes of the electroluminescent elements which are to be lighted up, thereby reducing the power consumption and increasing the response speed.

Driving system and method for an electroluminescent display

A combined digital TV decoding and optical recording system includes a transport stream demultiplexer to demultiplex at least one compressed multimedia stream from an MPEG transport stream having multiplexed compressed multimedia streams. A video encoder compresses a video stream to generate a second compressed video stream. A common system controller controls operations of the transport stream demultiplexer and the video encoder, and allocates portions of a memory to the transport stream demultiplexer and the MPEG video encoder based on respective memory requirements.

Video processing and optical recording using a shared memory

A real-time management method for manufacturing management and yield rate analysis integration. A plurality of yield rates relating to wafer products are summed and averaged for a historical yield rate. Multiple representational inline QC parameters are selected. A statistical process is implemented and, if no extreme value and collinear parameter exists and if analysis results satisfy normal distribution, multiple optimum inline QC parameters are selected from the representational inline QC parameters. Weights of each optimum inline QC parameter are calculated. A predicted yield rate is calculated according to the historical yield rate, weights, and a plurality of measurement and target values relating to the wafer products.

Real-time management systems and methods for manufacturing management and yield rate analysis integration

A dispatch integration method based on semiconductor manufacturing. When multiple tools are idle, idle messages are sent to a real-time dispatch system through a tool control system and a manufacturing execution system. The real-time dispatch system sorts tool parameters relating to tool efficiency based on a currently executed process using a principal component analysis method, defining weights of each tool according to the defined tool parameters and corresponding factor weights using a linear regression weight formula, calculating tool weights of each tool parameter using a linear regression weight formula, and determining a desired tool for dispatch according to the calculated tool weights.

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Hsinchu, Taiwan

Chien-Chung Chen