Macronix International Co., Ltd.

Novatek Microelectronics Corp.

Chien-Chung Chen

Shyi-Yuan Wu

Shih-Chin Lien

Ming-Tung Lee

Chien-Cheng Tu

Cheng-Chi Lin

Yin-Fu Huang

Chih-Chia Hsu

Po-Yao Ko

Chun-Po Huang

Po-Ju Lee

Hsu-Yu Huang

A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.

Data receiver and controller for DDR memory

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first well, a first heavily doping region, a field oxide, a first dielectric layer, and a conductive layer. The first well is disposed on the substrate, and the first heavily doping region is disposed in the first well. The field oxide is disposed on the first well and adjacent to the first heavily doping region. The first dielectric layer is disposed on the field oxide and covering the field oxide. The conductive layer is disposed on the first dielectric layer. The first well and the first heavily doping region have a first type doping.

Semiconductor structure and manufacturing method of the same

A semiconductor device and method of forming the semiconductor device are disclosed, where the semiconductor device includes additional implant regions in the source and drain areas of the device for improving Ron-sp and BVD characteristics of the device. The device includes a gate electrode formed over a channel region that separates first and second implant regions in the device substrate. The first implant region has a first conductivity type, and the second implant region has a second conductivity type. A source diffusion region is formed in the first implant region, and a drain diffusion region is formed in the second implant region.

MOS device and method of manufacturing the same

A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n&#x2212; (HVN&#x2212;) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n&#x2212; well and a source n&#x2212; well disposed in the HVN&#x2212; doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN&#x2212; ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.

Semiconductor device having reduced leakage current at breakdown and method of fabricating thereof

A low power differential signaling transmitter includes a switchable current source apparatus and a differential signaling generator coupled to the switchable current source apparatus. The switchable current source apparatus receives a first input voltage and a second input voltage, and generates a plurality of reference currents according to the first input voltage and the second input voltage. The differential signaling generator includes a plurality of first transistors, a plurality of second transistors, a first output voltage terminal and a second output voltage terminal. The on or off states of the first transistors and the second transistors are controlled by the reference currents. The first output voltage terminal outputs a first output voltage, and the second output voltage terminal outputs a second output voltage. The first output voltage and the second output voltage are determined according to the on or off states of the first and second transistors.

Low power differential signaling transmitter

A low voltage differential signaling (LVDS) transmitter receives a data signal, a data invert signal and a plurality of logic signals. The LVDS transmitter includes a first-stage differential signaling transmitting circuit and a second-stage differential signaling transmitting circuit. The first-stage differential signaling transmitting circuit receives the data signal and the data invert signal and has a first output terminal and a second output terminal. The second-stage differential signaling transmitting circuit is controlled by the logic signals, and has a third output terminal and a fourth output terminal respectively connected to the first output terminal and the second output terminal, so as to generate a needed pre-emphasis signal. When no pre-emphasis signal needs to be generated, the second-stage differential signaling transmitting circuit is controlled to be in disabled state.

Growing community of inventors

Pingtung County, Taiwan

Chien-Chung Chen