Taiwan Semiconductor Manufacturing Comp. Ltd.

Acer Inc.

Power Digital Delight Co., Ltd.

Easthill Industrial Co., Ltd.

Chien-Chung Chen

Jia-Ren Chang

Shiu-Ko JangJian

Chung-Wen Wu

Chun-Yuan Hsu

Chien-Wen Chiu

Yung-Hsieh Lin

Huai-Tei Yang

Feng-Ming Liu

Sen Mao

Hsin-Liang Lin

Yu-Sheng Wang

Ming-Chun Fang

Hung-Chang Chang

Yan-Jhih Huang

En-Ting Lee

Kun-El Chen

Po-Jen Tu

Kai-Meng Tzeng

Tzu-Chan Weng

Po-Zen Chen

Ruey-Ching Shyu

Kun-Ei Chen

Ming-Chun Yu

Chien-Yuan Chen

Chih-Hsueh Huang

Ying-Te Chuang

Mei-Chun Chiu

Hung-Lun Lu

A speaker module includes a casing, a speaker unit and a first vibration absorber. The speaker unit has a sound cavity. The speaker unit is disposed on a first wall of the casing. The speaker unit includes a diaphragm, a coil and a magnet, and the coil is configured to drive the diaphragm to vibrate relative to the magnet. The first vibration absorber is disposed in the sound cavity, and the first vibration absorber has a first natural frequency. When the ratio of the frequency of the diaphragm to the first natural frequency is greater than 0.781 and less than 1.28, the first vibration absorber is configured to absorb the vibration generated by the diaphragm to the casing.

Speaker module

An audio parameter optimizing method and a computing apparatus related to audio parameters. In the method, sound features of multiple sound signals are obtained. A wide dynamic range compression (WDRC) parameter corresponding to each of the sound signals is determined. Multiple data sets including the sound features and the corresponding WDRC parameters of the sound signals are created. The data sets are used to train a neural network, so as to generate a parameter inference model. The parameter inference model is configured to determine the WDRC parameter of a to-be-evaluated signal. Accordingly, a proper parameter could be provided.

Audio parameter optimizing method and computing apparatus related to audio parameters

An interconnection structure includes a first dielectric layer, a bottom conductive feature present in the first dielectric layer, a second dielectric layer present on the first dielectric layer, an aluminum-containing etch stop layer present between the first dielectric layer and the second dielectric layer, an upper conductive via present at least in the second dielectric layer and electrically connected to the bottom conductive feature, and at least one aluminum-containing fragment present at least at a bottom corner of the upper conductive via.

Interconnection structure and manufacturing method thereof

A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line on the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer; a second conductor; and an insulator between the first conductor and the second conductor, wherein the insulator surrounds the first conductor and the second conductor.

Semiconductor device including metal insulator metal capacitor

A metal-insulator-metal (MIM) capacitor includes a semiconductor substrate and a capacitor device. The capacitor device includes a first conductor upright on the semiconductor substrate, a second conductor upright on the semiconductor substrate, and an insulator disposed used for insulating the first conductor from the second conductor. In a method for fabricating the capacitor device, a mask including a test line pattern and a capacitor pattern with a first trench pattern and a second trench pattern is used to form a test line and the first conductor and the second conductor of the capacitor device, thereby decreasing the cost of for fabricating the MIM capacitor.

Metal insulator metal capacitor

An amplifier and an electronic device using the same are provided. The amplifier includes a first speaker, a second speaker, an acoustic box and at least one partition. The first speaker and the second speaker are disposed on a continuous surface inside the acoustic box. The partition is disposed on the continuous surface and interposed between the first speaker and the second speaker.

Amplifier and electronic device using the same

Formation methods of a semiconductor device structure are provided. A method includes forming a dielectric layer over a first conductive feature and a second conductive feature. The method also includes depositing a conformal layer in a first via hole and a second via hole in the dielectric layer. The method further includes removing the conformal layer in the second via hole. The dielectric layer remains covered by the conformal layer in the first via hole. In addition, the method includes etching the conformal layer in the first via hole and the dielectric layer until the first conductive feature and the second conductive feature become exposed through the first via hole and the second via hole, respectively. The method also includes forming a third conductive feature in the first via hole and a fourth conductive feature in the second via hole.

Formation method of interconnection structure of semiconductor device

A speaker module is provided. The speaker module includes a housing, a speaker unit, and a modulating unit. The housing has a main segment and an extension segment connecting to the main segment and extending away from the main segment, the main segment and the extension segment communicate with each other and form a chamber. The speaker unit is disposed in the housing in a position that is relative to the main segment. The modulating unit is arranged to correspond to the extension segment and is positioned in the housing. The shape of a cross section of the modulating unit is compatible with the shape of a cross section of the extension segment, and a length between the speaker unit and the modulating unit along the chamber is greater than 0.

Speaker module and electronic device using the same

A speaker device includes a first cabinet, a speaker unit, a second cabinet and a tube cabinet. The first cabinet is disposed in a casing and with a first chamber formed therein. The speaker unit is disposed in the first chamber. The second cabinet is connected to the casing and with an opening formed on the casing. The second cabinet has a second chamber formed therein and communicating with the opening. The tube cabinet connects the first cabinet and the second cabinet. The tube cabinet has a tube chamber formed therein and communicating with the first chamber and the second chamber. A sound generated by the speaker unit is enhanced in the first chamber, transmitted to the second chamber via the tube chamber and emitted out via the opening.

Speaker device with enhancement of bass and electronic device therewith

An integrated packaging structure is provided. In the package structure, an integrated component body has a first source region, a second source region, a first setting region, and a second setting region, which are separated from each other. A first MOSFET die and a second MOSFET die are located on the first setting region and the second setting region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed from the top surface and spaced apart from each other. A first source connection element is connected to the source electrode pad of the first MOSFET die and the first source region. A second source connection element is connected to the source electrode pad of the second MOSFET die and the second source region. A gate connection element is connected to the gate electrode pad and a gate region of the integrated component body.

Integrated packaging structure

A common-source type package structure is provided in the present invention. In the package structure, an integrated component body is configured a common-source pin region, a first arrangement region and a second arrangement region. The second and first arrangement regions are spaced apart from each other. A first MOSFET die and a second MOSFET are respectively located at the first and second arrangement region respectively, and have a top surface, a source electrode pad and a gate electrode pad. The source electrode pad and the gate electrode pad are exposed to the top surface and spaced apart from each other. A common-source connection element is connected to the source electrode pad and the common-source pin region. A gate connection element is connected to the gate electrode pad and a gate pin region of the integrated component body.

Common-source packaging structure

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Kaohsiung, Taiwan

Chien-Chung Chen