Sonics, Incorporated

Facebook Technologies, LLC

Chien-Chun Chou

Drew Eric Wingard

Wolf-Dietrich Weber

Stephen W Hamilton

Vida Vakilotojar

Krishnan Srinivasan

Jay S Tomlinson

Ian A Swarbrick

Nabil Masri

Michael Jude Meyer

Kamil Synek

Thomas Wayne O'Connell

Timothy A Pontius

Jeremy Chan

Kevin L Daberkow

Harutyun Aslanyan

Hervé Jacques Alexanian

Pascal Chauvet

Herve Alexanian

Jeffrey Allen Ebert

Alan Kamas

Sricharan Kasetti

Grigor Yeghiazaryan

Harutyan Aslanyan

Ruben Khazhakyan

Ian Andrew Swarbrick

Flow logic supports concurrency of multiple threads and/or tag IDs to be concurrently communicated across the interconnect while allowing the one or more target IP cores to be able to reorder incoming request transactions from the initiator IP core in a manner that is optimal for that target IP core while relieving that target IP core from having to maintain the sequential issue order of transaction responses to the incoming request transactions in the thread or tags when processed by the target IP core. The flow logic cooperates with the reorder storage buffers to control an operation of the reorder storage buffers as well as control issuance of at least the request transactions from the initiator IP core onto the interconnect in order to maintain proper sequential ordering of the transaction responses for the thread or tags when the transaction responses are returned back to the initiator IP core.

Reordering responses in a high performance on-chip network

An interconnect for an integrated circuit communicating transactions between initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect is generally described. The interconnect routes the transactions between the target IP cores and initiator IP cores in the integrated circuit. A first aggregate target of the target IP cores includes two or more memory channels that are interleaved in an address space for the first aggregate target in the address map. Each memory channel is divided up in defined memory interleave segments and then interleaved with memory interleave segments from other memory channels. An address map is divided up into two or more regions. Each interleaved memory interleave segment is assigned to at least one of those regions and populates the address space for that region, and parameters associated with the regions and memory interleave segments are configurable.

Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets

A method, apparatus, and system are described, which generally relate to an integrated circuit having an interconnect that implements internal controls. The interconnect in an integrated circuit communicates transactions between initiator Intellectual Property (IP) cores and target IP cores coupled to the interconnect. The interconnect implements logic configured to support multiple transactions issued from a first initiator IP core to the multiple target IP cores while maintaining an expected execution order within the transactions. The logic supports a second transaction to be issued from the first initiator IP core to a second target IP core before a first transaction issued from the same first initiator IP core to a first target IP core has completed while ensuring that the first transaction completes before the second transaction and while ensuring an expected execution order within the first transaction and second transaction are maintained. The logic does not include any reorder buffering.

Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering

A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary

A method and apparatus for transaction level modeling where communications occur between modules in the system that contain time annotations is described. An apparatus includes an initiator module, a target module, and a communications channel with each being modeled as an executable behavioral model. The communications channel transports burst information between the initiator module and the target module. The communications channel has a timing variable function to store timing variables and derive timing information associated with each individual transfer within a burst transaction during a simulation.

Methods and apparatuses for time annotated transaction level modeling

A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP core may include a memory coupled to the initiator IP core. Additionally, the interconnect can allow the integrated circuit to communicate transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect. A tag and thread logic can be configured to concurrently perform per-thread and per-tag memory access scheduling within a thread and across multiple threads such that the tag and thread logic manages tags and threads to allow for per-tag and per-thread scheduling of memory accesses requests from the initiator IP core out of order from an initial issue order of the memory accesses requests from the initiator IP core.

Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads

In general, methods and apparatus for implementing a Quality of Service (QoS) model are disclosed. A Quality of Service (QoS) contract with an initiating network device may be satisfied. A request may be received from the initiating network device in a first time less than or equal to an ordinal number times an arrival interval. The ordinal number signifies a position of the request among a group of requests. The request that has been serviced may be returned to the initiator in a second time less than or equal to a constant term plus the ordinal number times a service interval.

Method and apparatus for establishing a quality of service model

Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.

Various methods and apparatus for address tiling and channel interleaving throughout the integrated system

In an embodiment, an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and multiple target IP cores coupled to the interconnect. Two or more memory channels make up a first aggregate target of the target IP cores. The two or more memory channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop individual two-dimensional (2D) transactions that cross the memory channel address boundaries from a first memory channel to a second memory channel within the first aggregate target into two or more 2D transactions with a height value greater than one, as well as stride and width dimensions, which are chopped to fit within memory channel address boundaries of the first aggregate target.

Interconnect implementing internal controls

Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A method for providing performance instrumentation and analysis of the electronic design includes defining a first and second set of intended software instrumentation test points and an associated first and second set of performance analysis units. The method further includes instrumenting the first and second sets of software instrumentation test points and the associated first and second sets of performance analysis units to a first model and a second model, respectively. The method further includes creating a first and a second set of software instances associated with the first and second sets of intended software instrumentation test points and associated sets of performance analysis units during run time of a first simulation and a second simulation of the electronic design associated with the first model and second model, respectively.

Performance software instrumentation and analysis for electronic design automation

Various methods and apparatus are described for a memory scheduler. The memory scheduler couples to a target memory core that includes a bank of memories. The memory scheduler contains two or more configurable address tiling functions to transform an incoming address of data requested in a request to the target memory core to determine what physical addresses in the bank of memories will service the first request. The two or more configurable address tiling functions are programmable by a user to create two or more distinctly different memory regions in the target memory core. Each memory region has its own distinct tiling function based on configuration parameters 1) selected by the user and 2) stored in tiling registers in the memory scheduler. The multiple tiling functions are configured to operate concurrently in the integrated circuit.

Various methods and apparatus for address tiling

Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design having one or more bus interconnects. A relational database may have defined tables designed for interconnect analysis of transactions occurring between initiator intellectual property (IP) cores and target IP cores of the electronic design. A query tool may be configured to format input data to be stored in the defined tables, and have application programming interfaces to retrieve data from the defined tables based on performing a query. The query tool executes an algorithm based on the query to provide the interconnect analysis.

Method and system for a database to monitor and analyze performance of an electronic design

Various methods and apparatuses are described that provide instrumentation and analysis of an electronic design. A performance monitoring apparatus may be located on an interconnect of a fabricated integrated circuit. An event measurement module (EM) includes an event generator sub-module that generates monitoring events and event measurements associated with transactions between initiator intellectual property (IP) cores and target IP cores over the interconnect. The EM further includes a software visible register block that provides software access for controlling the EM on which one or more transactions to monitor and to configure one or more parameters associated with that transaction to track. The EM further includes a filtering sub-module that selects transactions to be monitored based on information received from the software. The performance counter module aggregates events and event measurements received from the EM into quantities of performance metrics associated with transactions between the IP cores over the interconnect.

Method and system to monitor, debug, and analyze performance of an electronic design

Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

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Saratoga, CA, United States of America

Chien-Chun Chou