Au Optronics Corporation

Chien-Chuan Ko

Meng-Chieh Tsai

Chih-Lung Lin

Chia-En Wu

Chun-Hung Kuo

Po-Chun Lai

A scan driver that includes a plurality of stages of scan driving circuits is provided. Each scan driving circuit includes: a driving transistor, including: a control terminal configured to receive a current-stage scan control signal, a first terminal configured to receive a first clock signal, and a second terminal configured to output a current-stage scan signal; an input stage circuit coupled to the driving transistor, where the input stage circuit includes: a first input transistor and a second input transistor, the first input transistor includes: a control terminal, a first terminal, and a second terminal, the second input transistor includes: a control terminal, a first terminal, and a second terminal, the control terminal of the first input transistor is configured to receive a next-stage scan signal, the control terminal of the second input transistor is configured to receive a previous-stage scan signal, and the second terminal of the first input transistor and the second terminal of the second input transistor are coupled to the control terminal of the driving transistor; a pull-down circuit, coupled to the driving transistor and configured to pull down the current-stage scan control signal and the current-stage scan signal; and a capacitor, coupled to the driving transistor and configured to maintain the current-stage scan control signal, where in a first scan mode, the first terminal of the first input transistor receives the first clock signal, and the first terminal of the second input transistor receives a first scan direction control signal; and in a second scan mode, the first terminal of the first input transistor receives a second scan direction control signal, and the first terminal of the second input transistor receives the first clock signal.

Scan driver and display apparatus using same

A shift register circuit includes a driving unit outputting a first scan signal according to a first clock signal; a pull up unit outputting a driving voltage according to one of a second scan signal and a third scan signal; a pull down unit pulling down voltage of an output end according to a second clock signal; a pull down control unit controlling the voltage of the output end and a driving node according to the first clock signal; a reset unit pulling down the voltage level of the driving node according to a touch-enable signal; and an electric storage unit adjusting the voltage of the driving node according to a touch-stop signal. When the touch-enable signal is enabled, the clock signals and the touch-stop signal are disabled, and when the touch-stop signal is enabled, the clock signals and the touch-enable signal are disabled.

Touch display apparatus and shift register thereof

A display driving method includes: performing a display scan function and a display stop function during a plurality of frame periods; during one frame period, outputting, alternately and sequentially along a scan direction, N scan signals according to K clock signals when performing the display scan function, wherein each of the scan signals has an enable period of a scan line, the clock signals sequentially have a delay, and each of the clock signals is a periodic signal with K delays as one period; providing a driving control signal and disabling the clock signals when performing the display stop function during a display stop period, wherein an initiation time position of the display stop period is changed based on an offset between two neighboring frame periods, and the neighboring frame periods have no overlapping or interlacing interval.

Display driving method and mobile apparatus thereof

A touch display apparatus is disclosed herein. The touch display apparatus has a timing controller outputting external signals; a touch driver for outputting touch driving signals according to the touch-enable signal; a scan driver having a multi-stage shift registers outputting scan signals, each shift register having a driving unit electrically connected to a driving node, outputting a first scan signal to an output end according to a clock signal; a pull-up unit outputting a driving voltage to the driving node according to a second scan signal; a pull-down control unit controlling a voltage level of the driving node according to the clock signal; a discharging unit adjusting the voltage level of the driving node according to a first control signal and the first scan signal, wherein the clock signal and the first control signal are in-phase periodic signals and respectively have a rising edge and a falling edge, the falling edge of the first control signal is ahead of that of the clock signal; and a pull-down unit electrically connected to the output end adjusting the voltage level of the output end, wherein the first control signal and the second control signal are complementary periodic signals.

A driving method for a display panel is disclosed. The display panel includes a plurality of gate lines. The driving method includes: driving the plurality of gate lines in a first preset sequence and a second preset sequence by turns, wherein the first preset sequence is defined from the first of the plurality of gate lines to the last of the plurality of gate lines, the second preset sequence is defined from the last of the plurality of gate lines to the first of the plurality of gate lines, and driving periods of each two adjacent gate lines partially overlap; and adjusting a voltage difference, between a high-voltage level and a low-voltage level, of each gate pulse provided to the gate lines when the gate lines are driven either in the first sequence or in the second sequence.

Driving method for display panel

A multi-phase gate driver includes a start/end signal generator circuit and X shift register modules. The start/end signal generator circuit is configured to sequentially output N start signals and N end signals according to a first control signal, a second control signal and N groups of clock signals. Each start and end signals have a delay relative to the previous one. Each group of clock signals includes a first clock signal and a second clock signal, which are inverted to each other. The X shift register modules are electrically coupled to the start/end signal generator circuit and each includes N shift register units. The Mth shift register unit of the first shift register module outputs a gate signal according to the Mth group of clock signals, the Mth start signal, and the gate signal outputted from the Mth shift register unit in the second shift register module.

Growing community of inventors

Hsin-Chu, Taiwan

Chien-Chuan Ko