Cadence Design Systems, Inc.

Chien-Chu Kuo

Oleg Levitsky

Dinesh Gupta

Hung-Chun Li

Ming-Chyuan Chen

Minghorng Lai

A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints

System and method of generating hierarchical block-level timing constraints from chip-level timing constraints

Aspects for clock tree synthesis of an integrated circuit include performing top-level clock tree synthesis, and estimating one or more block-level clock tree structures of the integrated circuit. The block-level clock tree structure is estimated based on a grid-based clock tree estimation, wherein each block is subdivided into one or more grids. The aspects further include merging of the estimated block-level clock tree structures with the top-level clock tree synthesis.

Method and system for clock tree synthesis of an integrated circuit

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San Jose, CA, United States of America

Chien-Chu Kuo