Taiwan Semiconductor Manufacturing Comp. Ltd.

Mediatek Corporation

Mediatek Singapore Pte. Ltd.

Hiwin Mikrosystem Corporation

Chien-Chih Lin

Shih-Hao Lin

Szu-Chi Yang

Chih-Chuan Yang

Kian-Long Lim

Hsin-Wen Su

Chia-Der Chang

Yu-Hua Huang

Cheng-Chou Hung

Tien-Chang Chang

Chun-Liang Chen

Tsung-Hung Lee

Chiyuan Lu

Yen-Ting Chen

Chih-Lin Wang

Feng-Ching Chu

Chia-Hao Pao

Chien-Tai Chan

Guan-Jie Shen

Chia-Wei Chen

Tzu-Ching Lin

Wen-Kai Lin

Ming-Lung Cheng

Chien-Hung Yeh

Chih-Hsuan Chen

Long-Jie Hong

Ping-En Cheng

Chia-Hung Chou

Chih Chieh Yeh

Chii-Horng Li

Li-Li Su

Wei-Ken Lin

An Chyi Wei

Chih-Chung Chiu

Hsiu-Hao Tsao

Chung-Shu Wu

Zheng Zeng

Tsai-Yu Huang

Tuoh Bin Ng

Jhih-Yang Yan

Shih-Chiang Chen

Chu-Wei Hu

Po-Kai Hsiao

Yin Wang

Cheng-Te Chi

Chang-Jhih Syu

Hsueh-Jen Yang

Yu-Ching Huang

Chao-Chin Teng

Chun-Te Li

Hsiang-Ju Wang

Chien-Chih Lee

Yun-Ju Pan

Yu-jiun Peng

Te-An Yu

Sheng-Hung Fan

Wei-Li Tsao

Cheng-Ting Ding

Allen Chien

A semiconductor device structure and a formation method are provided. The method includes forming a protruding structure over a substrate. The protruding structure has multiple sacrificial layers and multiple semiconductor layers, and the sacrificial layers and the semiconductor layers have an alternating configuration. The method also includes forming a gate stack to wrap a portion of the protruding structure. The method further includes forming an epitaxial structure abutting edges of the semiconductor layers. The formation of the epitaxial structure includes forming a lower semiconductor portion on a bottom of the recess and forming an upper semiconductor portion over the lower semiconductor portion. The upper semiconductor portion and the lower semiconductor portion are oppositely doped.

Structure and formation method of semiconductor device with epitaxial structures

A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Semiconductor device structure with gate stack and method for forming the same

A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Semiconductor structure

In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Semiconductor device and method

An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

SRAM speed and margin optimization via spacer tuning

Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

Transistors with multiple threshold voltages

A method of fabricating a device includes providing a fin having an epitaxial layer stack with a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes exposing lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers within a source/drain region of the semiconductor device. In some examples, the method further includes etching the exposed lateral surfaces of the plurality of dummy layers to form recesses and forming an inner spacer within each of the recesses, where the inner spacer includes a sidewall profile having a convex shape. In some cases, and after forming the inner spacer, the method further includes performing a sheet trim process to tune the sidewall profile of the inner spacer such that the convex shape of the sidewall profile becomes a substantially vertical sidewall surface after the sheet trim process.

Multi-gate device fabrication and structures thereof

A semiconductor structure includes: a semiconductor substrate; a first source/drain feature and a second source/drain feature over the semiconductor substrate; and semiconductor layers extending longitudinally in a first direction and connecting the first source/drain feature and the second source/drain feature. The semiconductor layers are spaced apart from each other in a second direction perpendicular to the first direction. The semiconductor structure further includes inner spacers each between two adjacent semiconductor layers; metal oxide layers interposing between the inner spacers and the semiconductor layers; and a gate structure wrapping around the semiconductor layers and the metal oxide layers.

Semiconductor structure and method for manufacturing the same

The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

Interface trap charge density reduction

In an embodiment, a method includes: forming a first gate stack and a second gate stack on a fin; etching the fin to form a recess in the fin between the first gate stack and the second gate stack; forming an epitaxial source/drain region in the recess, the forming including: forming a first layer lining sides and a bottom of the recess by dispensing silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess; and after forming the first layer, forming a second layer on the first layer by dispensing the silane, dichlorosilane, trichlorosilane, and hydrochloric acid in the recess, where each of the silane, dichlorosilane, trichlorosilane, and hydrochloric acid are dispensed at a first flow rate when forming the first layer and at a second flow rate when forming the second layer.

A method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin adjacent to the gate structure; and forming a source/drain region in the recess, the source/drain region including a first layer, a second layer, and a third layer, where forming the source/drain region includes performing a first epitaxy process under first process conditions to form the first layer in the recess, the first layer extending along surfaces of the fin exposed by the recess; performing a second epitaxy process under second process conditions to form the second layer over the first layer; and performing a third epitaxy process under third process conditions to form the third layer over the second layer, the third layer filling the recess, where the first processing conditions, the second process conditions and the third process conditions are different.

Fin field-effect transistor device and method of forming the same

A fin field-effect transistor (FinFET) structure and a method for forming the same are provided. The FinFET structure includes a first fin structure that protrudes from a first region of a substrate. A second fin structure protrudes from a second region of the substrate. Isolation regions cover lower portions of the first fin structure and the second fin structure and leave upper portions of the first fin structure and the second fin structure above the isolation regions. A first liner layer is positioned between the lower portion of the first fin structure and the isolation regions in the first region. A second liner layer covers the lower portion of the second fin structure and is positioned between the second fin structure and the isolation regions in the second region. The first liner layer and the second liner layer are formed of different materials.

Fin field-effect transistor structure and method for forming the same

Growing community of inventors

Hsinchu, Taiwan

Chien-Chih Lin