Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Actherm Inc.

Chien-Chih Kuo

Chen-Shien Chen

Chin-Yu Ku

Hon-Lin Huang

Wei-Li Huang

Chi-Cheng Chen

Lee-Chung Lu

Wen-Pin Hsieh

Sheng-Jier Yang

Jian-Yi Li

Hsien-Hsin Sean Lee

Kai-Ming Liu

Ze-Ming Wu

Yi-Cheng Lai

Shih Hsin Chen

Ching-Tai Tseng

A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation element partially covering the magnetic element. The semiconductor device structure further includes a conductive feature over the isolation element.

Semiconductor device structure with magnetic element

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an adhesive element between the magnetic element and the substrate. The adhesive element extends exceeding opposite edges of the magnetic element. The semiconductor device structure further includes an isolation element extending exceeding the opposite edges of the magnetic element. The isolation element partially covers a top surface of the magnetic element. In addition, the semiconductor device structure includes a conductive line over the isolation element.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The magnetic element has a first edge. The semiconductor device structure also includes an adhesive element between the magnetic element and the semiconductor substrate, and the adhesive element has a second edge. The semiconductor device structure further includes an isolation element extending across the magnetic element. The isolation element partially covers a top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The isolation element has a third edge, and the second edge is closer to the third edge than the first edge. In addition, the semiconductor device structure includes a conductive line over the isolation element.

A structure and a formation method of a semiconductor device are provided. The method includes forming an adhesive layer over a semiconductor substrate and forming a magnetic element over the adhesive layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes partially removing the adhesive layer such that an edge of the adhesive layer is laterally disposed between an edge of the magnetic element and an edge of the isolation element. In addition, the method includes forming a conductive line over the isolation element.

Structure and formation method of semiconductor device with magnetic element

A display device includes a data driver, a gate driver, a plurality of first pixel unit and a first low-pass filter. Each first pixel unit includes a first transistor, a first storage capacitor and a first liquid crystal capacitor. The first transistor is electrically coupled to the data driver and the gate driver and from which to receive the first display data and the gate control signal, respectively. The first transistor is configured to output the first display data according to the gate control signal. The first low-pass filter is configured to have its input electrode terminal electrically coupled to the second electrode terminal of one of the plurality of first transistor and its output electrode terminal electrically coupled to the second electrode terminal of the first liquid crystal capacitor of each of the first pixel units. An operation method for the display device is also provided.

Display device and operation method thereof

One or more systems and methods for a cell based hybrid resistance and capacitance (RC) extraction are provided. The method includes generating a layout for a semiconductor arrangement, performing a three-dimensional (3D) RC extraction on a target unit cell to obtain a 3D RC result including a coupling capacitance between unit cells, generating a 3D RC netlist based upon the 3D RC result, performing a 2.5 dimensional (2.5D) RC extraction on a peripheral cell to obtain a 2.5D RC netlist, and combining the 3D RC netlist with the 2.5D RC netlist to create a hybrid RC netlist for the layout. In some embodiments, the hybrid RC netlist is generated by stitching the coupling capacitance for at least one of the target unit cell, a repeating unit cell, or the peripheral cell together. In some embodiments, the 3D RC result for the target unit cell is stitched to the repeating unit cell.

System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction

A booster circuit for liquid crystal pixel data includes first, second and third signal control switches and a first storage capacitor. The first signal control switch is ON through a driving of a first control pulse and electrically coupled to a data voltage. The second signal control switch is ON through a driving of the first control pulse and electrically coupled to a reference voltage. The third signal control switch is ON through a driving of a second control pulse and electrically coupled to the data voltage. The first storage capacitor includes two terminals. The first storage capacitor has its first terminal electrically coupled to the reference voltage through the second signal control switch and electrically coupled to the data voltage through the third signal control switch and its second terminal electrically coupled to the data voltage through the first signal control switch and for providing an output voltage.

Panel driving circuit, booster circuit for liquid crystal pixel data and driving method thereof

A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. A structure includes a target diffusion region including a first edge with a first length and a second edge with a second edge perpendicular to the first length. A first stress-blocking dummy diffusion region is adjacent to the first edge, with no dummy diffusions regions therebetween. A second stress-blocking dummy diffusion region is adjacent to the second edge, with no dummy diffusion regions therebetween.

Dummy pattern design for reducing device performance drift

The invention discloses an analytical strip reading apparatus and the analytical strip used therein. The analytical strip reading apparatus comprises a housing, a monitor, a delivering device, an optical reader, a reaction signal reader and a control module. The analytical strip comprises at least one optically readable pattern which comprises identification information of the analytical strip.

Analytical strip reading apparatus and the analyical strip used therein

A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip.

A detecting strip reader with a removable firmware device, comprising a detecting strip reader and a firmware device. The firmware device comprises a first electrical connecting end, a database module, and an operation module, the firmware device being removably electrically connected to a second electrical connecting end in the detecting strip reader via the first electrical connecting end, wherein the characteristic of detecting strip reader is in that: a plurality of light reaction equations of detecting strips are saved in the database module, and when the first electrical connecting end of the firmware device receives an input signal from the second connecting end, the operation module selects one specific light reaction equation from the plurality of light reaction equations saved in the database module and performs the operation of the specific light reaction equation.

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Hsin-Chu, Taiwan

Chien-Chih Kuo