Inotera Memories, Inc.

Chien-Chi Lee

Chia-Ming Yang

Chung-Yuan Lee

Hung-Chang Liao

Jer-Chyi Wang

Chih-Yuan Hsiao

Hsin-Huei Chen

Ming-Chi Chao

Yao-Hsien Wang

Ping Kao

Chen-Kang Wei

Ming Yean

Kai-Lun Chiang

Yi-Wei Chuang

Wei-Ping Lee

Chao-Sung Lai

Hsiao-Lung Chiang

A memory cell with a recessed gate includes a semiconductor substrate, a shallow trench isolation, an active region, a gate electrode, a halogen-doped dielectric layer and at least a capacitor. The shallow trench isolation is disposed in the semiconductor substrate in order to define the active region. A source region and a drain region are respectively disposed on each end of the active region along a first direction. A gate trench is formed in the semiconductor substrate between the source region and the drain region, wherein the gate trench includes a sidewall portion and a curved-bottom surface. The curved-bottom surface has a convex profile when viewed from a cross-sectional view taken along a second direction perpendicular to the first direction. The gate electrode is disposed in the gate trench and the halogen-doped dielectric layer is disposed between the gate electrode and the semiconductor substrate.

Memory cell having a recessed gate and manufacturing method thereof

A DRAM with dopant stop layer includes a substrate, a trench-type transistor and a capacitor electrically connected to the trench-type transistor. The trench-type transistor includes a gate structure embedded in the substrate. A source doping region and a drain doping region are disposed in the substrate at two sides of the gate structure. A boron doping region is disposed under the source doping region. A dopant stop layer is disposed within the boron doping region or below the boron doping region. The dopant stop layer includes a dopant selected from the group consisting of C, Si, Ge, Sn, Cl, F and Br.

DRAM with dopant stop layer and method of fabricating the same

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Taipei, Taiwan

Chien-Chi Lee