Realtek Semiconductor Inc.

Tsinghua University

National Yang Ming Chiao Tung University

Chien-Cheng Liu

Yun-Chih Chang

Hsin-Fei Meng

Shu-Yi Kao

Cheng-Chung Chang

Sheng-Fu Horng

Yu-Chiang Chao

Ming-Zhi Dai

Sheng-Fu Hong

Yun-Ru Wu

Shih-Chih Liu

Wen-Hsing Liu

Jan-Hao Li

A method for performing power mesh optimization with the aid of additional wires and an associated apparatus are provided. The method includes: reading a clock cell definition file to obtain respective basic information of a plurality of clock cells in a circuit design; and according to the respective basic information of the plurality of clock cells, executing a power mesh optimization procedure, including: regarding any type of clock cells in multiple types of clock cells within the plurality of clock cells, classifying the clock cells into a plurality of sub-types according to respective sizes of the type of clock cells; and performing power mesh enhancement on respective clock cells of a set of sub-types within the plurality of sub-types, to add a set of additional wires crossing a set of original wires in an original power mesh at each clock cell of any sub-type of the set of sub-types.

Method and apparatus for performing power mesh optimization with aid of additional wires

A method of using a simulation software to generate a circuit layout, the method comprising: (A) determining a plurality of blocks on a circuit board, wherein each block of the plurality of blocks includes an operating space and a reserved space; (B) determining a size of the reserved space of each block of the plurality of blocks according to at least one specific condition;(C) determining whether to adjust the size of the reserved space of each block of the plurality of blocks according to at least one determining condition; and (D) when it is determined not to adjust the size of the reserved space in step (C), generating the circuit layout according to the size of the reserved space of each block of the plurality of blocks determined in step (B).

Method of using simulation software to generate circuit layout

A circuit structure is electrically connected to a power source. The circuit structure includes a first circuit module and a second circuit module. The first circuit module includes a first module power switch and a plurality of circuits. The first module power switch is electrically connected to the power source. The first circuit module has a first module current. The second circuit module includes a second module power switch and a plurality of circuits. The second power switch is electrically connected to the power source. The second circuit module has a second module current. A turn-on order of the first module power switch and the second power switch is determined based on the first module current and the second module current.

Circuit structure and power-on method thereof

The invention provides a label-free sensor that includes a substrate, a first electrode formed on the substrate, a second electrode formed on the substrate and spaced away from the first electrode, and a semiconductor layer formed on the substrate and being in contact with the first electrode and the second electrode. The semiconductor layer has a plurality of probe groups bonded to the semiconductor layer by functionalization, for sensing a coupling-specific substance having bonding specificity with the probe groups. The semiconductor layer is bonded with the probe groups, and the detection of detected object is performed in an instant, quick, rapid, and sensitive manner by measuring variation in electric current, avoiding the use of fluorescent reading equipment for reading fluorescent signals.

Label-free sensor

A first library cell and a second library cell each includes a plurality of metal layers, and a metal track direction of the odd metal layers of the first library cell is perpendicular to that of the odd metal layers of the second library cell. An integrated circuit design method applied to these library cells includes the steps of rotating the second library cell to cause the metal track direction of the odd metal layers of the second library cell to be parallel to that of the odd metal layers of the first library cell, and placing the first library cell and the second library cell in an identical integrated circuit design.

Integrated circuit design method applied to a plurality of library cells and integrated circuit design system thereof

The present invention discloses an organic field effect transistor and a manufacturing method thereof. The organic field effect transistor comprises a top-contact type or a bottom-contact type, and the manufacturing method thereof comprises the following steps: a substrate is provided, a metal gate is formed on the substrate, an inorganic insulating layer is formed on the substrate and the metal gate, a surface of the insulating layer is polished, an organic filler is filled in pores on the insulating layer as an insulating treatment, a modified layer is formed on the inorganic insulating layer, and finally an organic semiconductor layer, a source and a drain are formed. By combining the advantages of simply liquefied process of the organic material and the high stability of inorganic material, and operation conditions of control process, the present invention can achieve effectively that the device is high carrier mobility and high on/off ratio.

Growing community of inventors

Hsinchu, Taiwan

Chien-Cheng Liu