Advanced Semiconductor Engineering, Inc.

Other

Chien Cheng Liu

Meng-Jen Wang

Chi-Hao Chiu

Hsueh-Te Wang

Chih-Ming Chung

Tai-Yuan Huang

Chi-Ta Chuang

Chao Cheng Liu

Chih Ming Chung

Chih-Min Pao

Yao-Kai Chuang

Chao-Cheng Liu

Tsan-Sheng Huang

Chia Chien Hu

Sheng-Tai Tsai

Kuan Chen Wang

An intelligent teaching and tutoring test method is provided with a remote learning online test mode, a remote learning test paper test mode, a classroom teaching online test mode, and a classroom teaching test paper test mode. Based on the diversified data input methods and intelligent data analyzing process offered by an intelligent teaching and tutoring test system, the invention is a proprietary teaching and tutoring test method for different learners according to their differentiated individual learning situations so as to substantially enhance the learning efficiency of the learners.

Intelligent teaching and tutoring test method

A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad.

Circuit carrier and semiconductor package using the same

A semiconductor package includes a carrier, a chip, a stiffener and an encapsulant. The chip is disposed on the carrier. The stiffener is disposed around the chip, directly contacts the carrier, and is mounted on the carrier. The encapsulant is adapted to seal the chip and the stiffener.

Semiconductor package and method for manufacturing the same

A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip.

Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame

A package structure and a manufacturing method thereof are provided. The package structure includes a leadframe, a die, a solder layer and several connecting components. The leadframe includes a heat dissipation pad and several leads. The heat dissipation pad is disposed in a substantial center of the leadframe. The leads are surrounding the heat dissipation pad. The die having an active surface is disposed on the leadframe. The solder layer is disposed between the active surface and the heat dissipation pad. The connecting components are disposed between the active surface and the leads. The die is electrically connected to the leadframe through the solder layer and the connecting components.

Package structure and manufacturing method thereof

A flip chip on leadframe package and manufacturing method includes providing a leadframe having a plurality of inner leads; providing a chip having an active surface; forming a plurality of first bumps and at least one second bump on the active surface, the material of the first bumps is the same as the second bump, and the height of the second bump is lower than the first bumps; dipping the top of the first bumps in a flux, so that the second bump is not dipped with the flux; contacting the first bumps to the corresponding inner leads; proceeding with a reflow so that the first bumps are melted and connected to the corresponding inner leads, and the second bump is connected to the corresponding inner lead without being melted, to maintain a gap between the chip and the inner leads to prevent collapse of the first bumps.

Method for making flip chip on leadframe package

A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The flip chip includes an active surface, and at least one locking protrusion and a plurality of bumps formed on the active surface. The locking protrusion is correspondingly plugged into the locking hole to act as an anti-floating structure for the flip chip package. When the solders are used for connecting the bumps with the leads by reflowing, the anti-floating structure will prevent the flip chip from floating up, and the solders will not generate necking after reflowing.

Flip chip package with anti-floating structure

A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed '&#x3a9;'-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.

Semiconductor package with a flip chip on a solder-resist leadframe

A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.

Quad flat flip chip package and leadframe thereof

A flip-chip type quad flat package and a leadframe. The leadframe comprises a bump-connecting area and a non-connecting area. The maximum width of the bump-connecting area is larger than the width of the non-connecting area. A bump is limited to the bump-connecting area after performing a reflow process so that the bumps are prevented from collapsing, the manufacturing cost is reduced and the process is simplified.

Flip-chip type quad flat package and leadframe

A quad flat flip chip packaging process and a leadframe therefor are provided. A sacrificial film is attached on the leads of the leadframe for limiting the extent of bumps when formed and saving the manufacturing cost. Besides, the sacrificial film can be removed from the leadframe after a reflow step. Thus, the delamination between the molding compound material and the leads can be prevented during the molding step.

Quad flat flip chip packaging process and leadframe therefor

A package structure with a heat spreader and manufacturing method thereof is disclosed. The package structure includes a substrate, a ground pad, a heat spreader, a non-conductive adhesive layer, and a pre-solder layer. A die is seated on the substrate, and the ground pad is disposed on the surface of the substrate. The manufacturing method of the package structure includes the following steps: (a) providing the substrate; (b) forming the pre-solder layer on the ground pad by solder paste printing; (c) forming the non-conductive adhesive layer on the substrate surface for being adjacent to the pre-solder layer by adhesive dispensing; (d) disposing the heat spreader onto the non-conductive layer and the pre-solder layer; and (e) heating the non-conductive adhesive layer for solidification and continuing to heat the pre-solder layer for solder reflow so that the heat spreader is adhered to the substrate via the non-conductive adhesive layer and coupled to the ground pad via the pre-solder layer.

Growing community of inventors

Kaohsiung, Taiwan

Chien Cheng Liu