Eever Technology, Inc.

Nvidia Corporation

Etron Technology, Inc.

Chien-Cheng Kuo

Shih-Min Hsu

Chih-Hung Huang

Chih-Kao Chen

Shao-Hung Chen

Huan-Hsiang Shen

A universal serial bus (USB) type C transmission line includes a host-to-host bridge, a first multiplexer, and a second multiplexer. When a first device and a second device are coupled to the first multiplexer and the second multiplexer respectively, the first multiplexer determines whether the first device is a host or a slave device and the second multiplexer determines whether the second device is another host or another slave device, and the first device optionally communicates with the second device through the host-to-host bridge, the first multiplexer, and the second multiplexer, or through the first multiplexer and the second multiplexer according to determination results of the first multiplexer and the second multiplexer.

Universal serial bus type C transmission line and transmission device

A USB 3.0 host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit is used for transmitting data at a first transmission speed. A default state of the super speed circuit is turning-off. The non-super speed circuit is used for transmitting data at a second transmission speed, a third transmission speed, or a fourth transmission speed. The first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. The control module is used for detecting whether a USB peripheral device is connected to the USB 3.0 host, and controlling turning-on and turning-off of the super speed circuit.

Universal serial bus (USB) 3.0 compatible host with lower operation power consumption and method for reducing operation power consumption of a USB 3.0 compatible host

A USB 3.0 compatible host with low power consumption includes a super speed circuit, a non-super speed circuit, and a control module. The super speed circuit transmits data at a first transmission speed and the non-super speed circuit transmits data at a second transmission speed, a third transmission speed, or a fourth transmission speed wherein the first transmission speed is faster than the second transmission speed, the third transmission speed, and the fourth transmission speed. Further, the control module is coupled to the super speed circuit and the non-super speed circuit for determining to turn on or off the super speed circuit of the USB 3.0 compatible host, during the USB 3.0 compatible host being connected to a USB 3.0 compatible peripheral device, based on whether transmission data quantity between the USB 3.0 compatible host and the USB 3.0 compatible peripheral device is greater than a predetermined value.

Universal serial bus USB 3.0 compatible host with lower operation power consumption and method for reducing operation power consumption of a USB compatible 3.0 host

A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial bus host. Then, a packet identification (PID) unit identifies a packet identification of a start of each frame and a first period between two consecutive packet identifications according to the series of digital data. A count comparator is used for generating a calibration signal to calibrate an output frequency of an oscillator according to the first period.

Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof

A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code executed by the pipelined CPU are being fetched respectively by each corresponding pipeline for enabling the code to be executed without stall so that the number of cycles required to execute the code can be reduced effectively. Moreover, the multiple pipelines can save more cycles when the number of stages in one pipeline is large.

Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths

An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.

Growing community of inventors

Taipei, Taiwan

Chien-Cheng Kuo