Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Chien-Chang Su

Hsien-Hsin Lin

Tsz-Mei Kwok

Yi-Fang Pai

Chii-Horng Li

Hsueh-Chang Sung

Kuan-Yu Chen

Chien-I Kuo

Chun Hsiung Tsai

Ying-Wei Li

Yen-Ru Lee

King-Yuen Wong

Li-Li Su

Heng-Wen Ting

Jung-Chi Tai

Shih-Hsien Huang

Che-Hui Lee

Kei-Wei Chen

Tung Ying Lee

Yasutoshi Okuno

Pei-Ren Jeng

Su-Hao Liu

Da-Wen Lin

Chien-Tai Chan

Wang-Chun Huang

Lilly Su

Ta-Chun Ma

Cheng-Hsiung Yen

Jung-Jen Chen

Yee-Chia Yeo

Ming-Hua Yu

Weng Chang

Chun-Feng Nieh

Yen-Chun Lin

Meng-Yueh Liu

Chia-Yu Lu

Chih-Chiang Chang

Chii-Ming M Wu

Pang-Yen Tsai

Chien-Wei Lee

Wen-Sheh Huang

Yan-Ting Lin

Hung-Yin Tsai

Chih-Yun Chin

Yuh-Da Fan

Yuan-feng Chao

Tsung-Hung Li

Ping-Yin Liu

Chin-Hon Fan

Bang-Ting Yan

Chien-wei Lee

Yi-Kai Tseng

Tzu-Chun Tseng

Chun-Hao Hsieh

Chih Teng Hsu

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source/drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source/drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.

Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction

An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.

FETs and methods of forming FETs

A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Nanosheet semiconductor device and method for manufacturing the same

An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

Integrated circuits having source/drain structure and method of making

A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.

Semiconductor method and device

FETS and methods of forming FETS

A semiconductor device includes a semiconductor substrate, at least one first isolation structure, at least one second isolation structure, a source structure, a drain structure and a plurality of semiconductor fins. The first isolation structure and the second isolation structure are located on the semiconductor substrate. The source structure is located on the semiconductor substrate and the first isolation structure, in which at least one first gap is located between the source structure and the first isolation structure. The drain structure is located on the semiconductor substrate and the second isolation structure, in which at least one second gap is located between the drain structure and the second isolation structure. The semiconductor fins protrude from the semiconductor substrate, in which the semiconductor fins are spaced apart from each other, and connect the source structure and the drain structure.

FinFET device and method for fabricating the same

The integrated circuit includes a gate structure over a substrate. The integrated circuit further includes a first silicon-containing material structure in a recess adjacent to the gate structure. The first silicon-containing material structure includes a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in contact with the substrate. The first silicon-containing material structure further includes a second layer over the first layer, wherein an entirety of the second layer is co-planar with or above the top surface of the substrate. A first region of the second layer closer to the gate structure is thicker than a second region of the second layer farther from the gate structure. Thickness is measured in a direction perpendicular to the top surface of the substrate.

Integrated circuits having source/drain structure

A method for manufacturing a semiconductor device includes forming a fin structure having a top face and a first side face and a second side face opposite to the first side face, forming a lower cover layer over the first and second side faces, forming an upper cover layer over the first and second side faces, the upper cover layer being spaced apart from the lower cover layer so that exposed regions of the first and second side faces are formed between the lower cover layer and the upper cover layer, and forming first and second semiconductor layers over the exposed regions of the first and second side faces, respectively.

Semiconductor device including fin structure with two channel layers and manufacturing method thereof

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Kaohsiung, Taiwan

Chien-Chang Su