Taiwan Semiconductor Manufacturing Comp. Ltd.

Elite Semiconductor Memory Technology, Inc

Other

Mosel Vitelic Corporation

Chien Chang

Hung-Yi Huang

Chih-Wei Chang

Sung-Li Wang

Shuen-Shin Liang

Chia-Hung Chu

Hsu-Kai Chang

Chih-wei Chang

Min-Hsiu Hung

Yi-Hsiang Chao

Kan-Ju Lin

Keng-Chu Lin

Lin-Yu Huang

Ming-Hsing Tsai

Chun-Hsien Huang

Ken-Yu Chang

Chun-I Tsai

Chi-Hung Chuang

Kai-Yi Chu

Chih-Shiun Chou

Wei-Yip Loh

Hong-Mao Lee

Yan-Ming Tsai

Mao Song Tseng

Yi-Ning Tai

Harry Chien

Tzu Pei Chen

Pei Jey Huang

Ming Chien Huang

Hsing Huang Hsieh

Tai Min Chang

TaiMin Chang

A semiconductor structure and method of forming a semiconductor structure are provided. In some embodiments, the method includes forming a gate structure over a substrate. An epitaxial source/drain region is formed adjacent to the gate structure. A dielectric layer is formed over the epitaxial source/drain region. An opening is formed, the opening extending through the dielectric layer and exposing the epitaxial source/drain region. Sidewalls of the opening are defined by the dielectric layer and a bottom of the opening is defined by the epitaxial source/drain region. A silicide layer is formed on the epitaxial source/drain region. A metal capping layer including tungsten, molybdenum, or a combination thereof is selectively formed on the silicide layer by a first deposition process. The opening is filled with a first conductive material in a bottom-up manner from the metal capping layer by a second deposition process different from the first deposition process.

Semiconductor device structure and method for forming the same

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

Fin field-effect transistor device and method of forming the same

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

Semiconductor structure and method of forming the same

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a layer of dielectric material over the gate structure, a source/drain (S/D) contact layer formed through and adjacent to the gate structure, and a trench conductor layer over and in contact with the S/D contact layer. The S/D contact layer can include a layer of platinum-group metallic material and a silicide layer formed between the substrate and the layer of platinum-group metallic material. A top width of a top portion of the layer of platinum-group metallic material can be greater than or substantially equal to a bottom width of a bottom portion of the layer of platinum-group metallic material.

Contact structure for semiconductor device

The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a bottom metal line in a first interlayer dielectric layer, forming a second interlayer dielectric layer over the bottom metal line, exposing a top surface of the bottom metal line, increasing a total surface area of the exposed top surface of the bottom metal line, forming a conductive via over the bottom metal line, and forming a top metal line over the conductive via.

Interconnect structure and manufacturing method for the same

The present disclosure provides an interconnect structure, including a first interlayer dielectric layer, a bottom metal line including a first metal in the first interlayer dielectric layer, a conductive via including a second metal over the bottom metal line, wherein the second metal is different from the first metal, and the first metal has a first type of primary crystalline structure, and the second metal has the first type of primary crystalline structure, a total area of a bottom surface of the conductive via is greater than a total cross sectional area of the conductive via, and a top metal line over the conductive via, wherein the top metal line comprises a third metal different from the second metal.

A duty cycle correction circuit comprises a duty cycle detector, a filter, an amplifier, a charge pump, a control circuit, and a duty cycle corrector. The duty cycle detector is configured to generate a first pair of control signals according to a pair of internal clock signals. The filter is configured to obtain average voltages of the first pair of control signals. The amplifier is configured to compare output voltages of the filter for generating an enable signal, and the control circuit is configured to generate a selection signal according to the enable signal. The charge pump is configured to generate a second pair of control signals according to the enable signal and the selection signal, and the duty cycle corrector is configured to receive a pair of external clock signals, the first pair of control signals, and the second pair of control signals for generating the pair of internal clock signals with a corrected duty cycle.

Circuit and method for providing a corrected duty cycle

A DRAM bit line precharge voltage generator comprises a first amplifier having a first current source and comparing a first voltage with a precharge voltage to control a first PMOS transistor, a second amplifier having a second current source and comparing a second voltage with the precharge voltage to control a second PMOS transistor, a third amplifier having a third current source and comparing a third voltage with the precharge voltage to control a first NMOS transistor, and a fourth amplifier having a fourth current source and comparing the first voltage with the precharge voltage to control a second NMOS transistor. The precharge voltage feedbacks from an output node connected between the second PMOS transistor and the first NMOS transistor. The DRAM bit line precharge voltage generator with a low-frequency pole provided by the first amplifier, the first PMOS transistor, the fourth amplifier, and the second NMOS transistor exhibits the characteristics of robustness, low standby current and low-output impedance.

DRAM bit line precharge voltage generator

A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for blocking ions from diffusing into the epitaxial layer, and a deposition layer formed on the ion barrier layer. Thereby, the deep trench of the super-junction device is formed by performing an etch process on the epitaxial layer via the hard mask structure. The hard mask structure can effectively prevent ions from diffusing into the epitaxial layer, so as to avoid unusual electrical property.

Hard mask structure for deep trenched super-junction device

A data refresh method of a pseudo static random access memory is implemented by the following procedure. First, an address string and a refresh signal are provided, in which the address string is used for the reference of data reading and writing positions. Secondly, within at least one address of the address string, the active time of a word line of the PSRAM is set to be equivalent to or less than a half of the period of the refresh signal. Then, refreshing performs while the word line is off, and reading and writing are performed while the word line is active. If writing is requested while the word line is off, the writing will be performed when an address transition detection signal ATD switches to the high level in the next address.

Pseudo static random access memory and data refresh method thereof

A chair and hand truck comprising a seat, a cross frame and a back frame with a back cushion, the seat having hangers for pivotal members to combine the cross frame with the seat and a bolt holes for a pivotal member to combine the back frame with the seat in a right angle, the cross frame having a U-shaped rod frame and a rectangular rod frame pivotally combined together like an X, the cross frame possible to become feet of a chair or a pull rod of a hand truck when it is transformed in different ways.

Chair and hand truck

Bench

A multi-function chair comprising a fore leg frame and a hind leg frame combined movably intercrossing each other to stand on the ground as a chair or to be folded in a straight line as a light duty truck with casters to stand and move on the ground.

Multi-function chair

Growing community of inventors

Hsinchu, Taiwan

Chien Chang