Omnivision Technologies, Inc.

Chien-Chan Yeh

Ying-Chih Kuo

Wei-Feng Lin

Chun-Sheng Fan

Teng-Sheng Chen

Cheng-Fang Chiu

A surface-mount device platform includes a surface-mounting region, a connection region, and a bendable region therebetween, each including a respective part of a base substrate. The base substrate includes electrically-conductive layers interspersed with electrically-insulating build-up layers. Each of the surface-mounting region, the connection region, and the bendable region spans between a bottom substrate-surface and a top substrate-surface of the base substrate. The surface-mounting region further includes an electrically-insulating first top rigid-layer, and device bond-pads exposed on a top surface of the first top rigid-layer facing away from the top substrate-surface in the surface-mounting region. The connection region further includes an electrically-insulating second top rigid-layer and a plurality of connector bond-pads each exposed on a top surface of the second top rigid-layer facing away from the top substrate-surface in the connection region, and electrically connected to a respective device bond-pad via at least one of the electrically conductive layers.

Surface-mount device platform and assembly

A cavityless chip-scale image-sensor package includes a substrate, a microlens array, and a low-index layer. The substrate includes a plurality of pixels forming a pixel array. The microlens array includes a plurality of microlenses each (i) having a lens refractive index, (ii) being aligned to a respective one of the plurality of pixels and (iii) having a non-planar microlens surfaces facing away from the respective one of the plurality of pixels. The low-index layer has a first refractive index less than the lens refractive index. The low-index layer also includes a bottom surface, at least part of which is conformal to each non-planar microlens surface. The microlens array is between the pixel array and the low-index layer.

Cavityless chip-scale image-sensor package

A method for fabricating an image-sensor chip-scale package includes bonding, with temporary adhesive, a glass wafer to a device wafer including an array of image sensors. The method also includes forming an isolated-die wafer by removing, from the device wafer, each of a plurality of inter-sensor regions each located between a respective pair of image sensors of the array of image sensors. The isolated-die wafer includes a plurality of image-sensor dies each including a respective image sensor, of the array of image sensors, bonded to the glass wafer. The method also includes encapsulating the isolated-die wafer to form an encapsulated-die wafer; removing, from each of the plurality of image-sensor dies, a respective region of the glass wafer covering the respective image sensor; and singulating the encapsulated-die wafer.

Image-sensor chip-scale package and method for manufacture

An image sensor package includes a transparent material, and a substrate adhered to the transparent material. An image sensor is disposed on or within the substrate so that the image sensor is disposed between the substrate and the transparent material to receive light from an optical side of the image sensor package through the transparent material. A solder mask dam is disposed between the substrate and the transparent material to form a gap between the image sensor and the transparent material, and the solder mask dam is structured to indicate an orientation of the image sensor, when the image sensor is viewed from the optical side.

Solder mask dam design

A chip comprises a semiconductor substrate having a first side and a second side opposite to the first side, a plurality of conductive metal patterns formed on the first side of the semiconductor substrate, a plurality of solder balls formed on the first side of the semiconductor substrate, and at least one code pattern of a first group and at least one code pattern of a second group formed on the first side of the semiconductor substrate in a space free from the plurality of conductive metal patterns and the plurality of solder balls, wherein the code patterns are visible from a backside of the chip, and wherein a tracing number of the chip is represented by the code patterns.

Growing community of inventors

Hemei, Taiwan

Chien-Chan Yeh