Taiwan Semiconductor Manufacturing Comp. Ltd.

Chien-An Lai

Chung-Cheng Chou

Yu-Der Chih

Zheng-Jun Lin

Pei-Ling Tseng

Hsu-Shun Chen

Wen-Yu Ku

Joseph Wu

A memory device includes an array of resistive memory cells with a plurality of word lines connected to the array of resistive memory cells. A voltage compensation controller is configured to determine a word line voltage to be applied to a selected word line of the plurality of word lines. A word line driver is configured apply the determined word line voltage to the selected word line.

RRAM voltage compensation

A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.

RRAM circuit and method

A memory circuit includes a bias voltage generator including a bias voltage node, an activation voltage generator including a resistive device, and a first amplifier, a drive circuit including a second amplifier including an input terminal coupled to the bias voltage node, and a resistive random-access memory (RRAM) array. The activation voltage generator and the first amplifier are configured to generate a portion of a bias voltage level on the bias voltage node based on a resistance of the resistive device, and the drive circuit is configured to output a drive voltage having the bias voltage level to the RRAM array.

A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

Memory device

A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.

A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first current path configured to receive a first current from a current source, and output a bias voltage based on a voltage difference generated from conduction of the first current in the first current path. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to conduct a second current responsive to the drive voltage.

A method includes receiving a semiconductor wafer into a chamber; generating a plasma within the chamber to accelerate particles toward the semiconductor wafer; generating a magnetic field above the semiconductor wafer by an electromagnetic structure contained within the chamber, wherein the electromagnetic structure comprises a plurality of electromagnetic elements; and adjusting the magnetic field, wherein the adjusting of the magnetic field includes moving positions of each of the plurality of electromagnetic elements independently.

Systems and methods for a tunable electromagnetic field apparatus to improve doping uniformity

Systems and methods for improving doping and/or deposition uniformity using a tunable electromagnetic field generation device are provided. In an exemplary embodiment, the system includes a chamber configured to contain a semiconductor wafer, a plasma generator, and a gas inlet, and an exhaust gas outlet. The gas inlet permits a controlled flow of a gas into the chamber through a wall of the chamber and the exhaust gas outlet permits exhausting of gas from the chamber. The system further includes a wafer support structure configured to support the semiconductor wafer during a doping or deposition process and an electromagnetic structure positioned within the chamber and at least partially surrounding an upper surface of the wafer support structure.

Growing community of inventors

Hsinchu, Taiwan

Chien-An Lai