Hitachi, Ltd.

Other

Chiemi Hashimoto

Shuji Ikeda

Takashi Hashimoto

Toshiaki Yamanaka

Kousuke Okuyama

Yasuko Yoshida

Keiichi Yoshizumi

Kazushi Fukuda

Soichiro Hashiba

Kazuo Yoshizaki

Fumiyuki Kanai

Kazushi Tomita

Tsuyoshi Tabata

Koichi Imato

Kohji Yamasaki

Motoko Kawashima

Junichi Takano

Mitsugu Oshima

Akihiro Shimizu

Masahiro Moniwa

Keizo Kawakita

Yasuhiko Kawashima

Hiroyasu Ishizuka

Disclosed are a semiconductor integrated circuit device and a method of manufacturing the same capable of realizing the two-level gate insulator process for the DRAM without increasing the number of manufacturing steps and that of photomasks. After forming a gate electrode of a MISFET which constitutes a memory cell in a memory array region on a semiconductor substrate, the substrate is subjected to thermal treatment (re-oxidation process). At this time, since bird's beak of the thick gate insulating film formed below the sidewall portion of the gate electrode penetrates into the center of the gate electrode, a gate insulating film thicker than the gate insulating film before the re-oxidation process is formed just below the center of the gate electrode. Meanwhile, since the gate electrode in the peripheral circuit region has a gate length longer than that of the gate electrode in the memory array region, the thickness of the gate insulating film just below the center thereof is almost equal to that before the re-oxidation process.

Semiconductor integrated circuit device and manufacturing method thereof

A SRAM having its memory cell constructed to include transfer MISFETs to be controlled by word lines and a flip-flop circuit having driver MISFETs and load MISFETs. Plate electrodes of large area fixed on predetermined power source lines are arranged over the load MISFETs such that the plate electrodes over the offset region of the load MISFETs are formed with an opening. A silicon nitride film having a thickness permeable to hydrogen but not to humidity is formed over the transfer MISFETs and the driver MISFETs formed over the main surface of a semiconductor substrate and the load MISFETs formed of a polycrystalline silicon film deposited on the driver MISFETs.

Semiconductor integrated circuit device having capacitance element and

Semiconductor integrated circuit device and process of manufacturing the

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Koganei, Japan

Chiemi Hashimoto