Amlogic Co., Limited

Mediatek Corporation

Silicon Image Gmbh

Hyperband Communication, Inc.

Parade Technologies, Ltd.

Mediatek USA Inc.

Uniband Electronic Corp.

Sogics Corporation Limited

Hyperband Communications, Inc.

Silicon Communications Lab, Inc.

Chieh-Yuan Chao

Yiping Fan

Hongyu Li

Shu-Sun Yu

Ming Shi

Weicheng Zhang

Kanyu Cao

Wei-Hua Zou

Yuming Cao

Chao Shi

Syang-Myau Hwang

Lei Wang

Hao Zhu

Dongyun Lee

Sifen Luo

Shou-Po Shih

Kai Fan

Chen-Yi Chang

Haihong Zhao

Jinguo He

Jen-Dong Yuh

Tung-Shan Chen

Xiang OuYang

Yu-Jen Wu

Xiaoniu Luo

Jenghung Tsai

Arnaud David Nicolas Muller

Jinbao Lan

An electronic device includes two multiplexer branches, a modulation circuit, and an output interface coupled to the modulation circuit and two multiplexer branches. A first multiplexer branch generate s first output signal from a first selection signal, a first inverse signal, and a first input signal. The first inverse signal is substantially complementary to the first selection signal. A second multiplexer branch generates a second output signal from the first selection signal, the first inverse signal, and a second input signal. The modulation circuit generates a logic output signal from the first input signal and the second input signal, independently of the first selection signal and the first inverse signal. The output interface generates a multiplexed signal tracking one of the first input signal and the second input signal based on the first output signal, the second output signal, and the logic output signal.

Floating voltage suppression in high speed multiplexers

Method and apparatus for a display bridge with support for multiple display interfaces are disclosed. The novel display bridge comprises a predriver configured to provide data input signals. A shared output driver is configured to receive the data input signals and provide output display signals compatible for driving MIPI-DSI, EDP, or LVDS displays. A regulator and current source is coupled to the shared output driver configured to regulate the shared output driver operating voltage and provide a current source for the shared output driver. A shared termination output coupled to the shared output driver is configured to provide termination resistance for the output display signals and termination voltage for the termination resistance.

Display bridge with support for multiple display interfaces

A switched capacitor digital-to-analog converter ('DAC') for converting a digital input code to an analog signal comprises a switched capacitor array and a reset switch having a first end and a second end. The digital input code is inputted to the switched capacitor array. The switched capacitor array is connected to a summation node. The first end of the reset switch is connected to the summation node and the second end of the reset switch is connected to a common mode voltage. The reset switch is closed after a plurality of sampling cycles. The analog signal is provided based on a summation voltage at the summation node.

Switched capacitor digital-to-analog converter

A modem for communicating application data over a voice channel comprises an adaptive modulator, a mixer, and a vocoder. The adaptive modulator modulates application data as a function of a source application of the application data and feedback information of the voice channel. The modulated data is inputted to the mixer. The vocoder processes the mixed data for transmission through the voice channel.

Data transmissions over a voice channel

A dynamic element matching method for a multi-unit-element digital-to-analog converter having unit elements comprises several steps. An element selection probability is determined as a function of a number of the unit elements and a digital signal. Next, loop filter output signals are generated as a function of the determined element selection probability and control signals for the unit elements. Certain ones of the unit elements are selected as a function of the generated loop filter output signals. The selected certain ones of the unit elements are activated for output of the converter.

Dynamic element matching methods and apparatuses

A transmitter, comprises: a first branch for providing a positive output having a first set of serially-connected transistors; a second branch for providing a negative output having a second set of serially-connected transistors; and a biasing circuit, wherein the biasing circuit generates a first biasing voltage and a second biasing voltage as a function of the positive output, the negative output, and a predefined threshold voltage, and wherein the first biasing voltage, the second biasing voltage, and a differential input signal drive the first set of serially-connected transistors and the second set of serially-connected transistors.

Electrostatic discharge device gate biasing for a transmitter

Some embodiments of the present invention provide a method and apparatus for a Vernier ring time to digital converter having a single clock input and an all digital circuit that calculates a fixed delay relationship between a set of slow buffers and fast buffers. A method for calibrating a Vernier Delay Line of a TDC, comprising the steps of inputting a reference clock to a slow buffer and to a fast buffer, determining a delay ratio of the slow buffer and fast buffer; and adjusting the delay ratio of the slow buffer and fast buffer to a fixed delay ratio value wherein an up-down accumulator generates control signals to adjust the slow buffer.

Method and apparatus for Vernier ring time to digital converter with self-delay ratio calibration

An adaptive digital phase locked loop comprises: a digital configurable phase detector for receiving a reference signal and a feedback signal and for generating a detection signal indicative of a phase/frequency difference between the reference signal and the feedback signal; a configurable digital loop filter for filtering the DPFD detection signal; a digital locking monitor for monitoring polarity transitions of the detection signal and adaptively switching the locking modes and DCO tuning resolution; and a DCO for generating the feedback signal as a function of the detection signal.

Digital phase locked loop

A method for digital phase detection, comprises the steps of: providing a reference clock; receiving a feedback clock; determining a timing difference between the reference clock and the feedback clock; determining a polarity that indicates the leading or lagging relationship between the reference clock and the feedback clock; adaptively selecting one of at least two operating modes for generating a quantized level indicative of the timing difference, wherein in a first operating mode the quantized level is a constant maximum value and wherein in a second operating mode the quantized level is proportional to the timing difference; and generating a digital phase detection output as a combination of the polarity and the quantized level.

Digital phase and frequency detector

A transceiving system utilizing a shared filter module is provided. The shared filter module is selectively filtering signals in a first band in a first mode and a second band in a second mode. The first mode is a receiver mode whereas the second mode is a transmission mode. The shared filter module comprises a compound filter comprising two low pass filters and a coupling controller to manage input and output wiring of the low pass filters. When the coupling controller is enabled in the first mode, the compound filter acts as a bandpass filter. When the coupling controller is disabled, the compound filter acts as two independent low pass filters.

Transceiving system and compound filter

A spread spectrum receiver whose de-spreading process based on transformed spreading codes is provided. Instead of de-spreading with original spreading codes, this approach de-spreads received signal with the spreading codes transformed from the original codes in order to eliminate the negative impact of system impairments such as frequency offset to a spread spectrum receiver. Before de-spreading with the transformed code, the received signal goes through the same transformation as the original codes do. After a transformation, the transformed codes may exist some undesirable property such as spreading code having DC content. An approach is given to cancel unwanted side effects relating the transformed spreading codes. The approaches are very effective for spread spectrum system based on frequency modulation scheme such as MSK. For this kind of system, the frequency offset translates to DC offset after the transformation and the DC offset can be cancel since the DC property of the transformed spreading code is known in advance.

Receiver based method for de-spreading of spread spectrum signal

Fast settling circuits and methods designed to align input signal amplitude level and to remove DC offset voltages with minimal loss of low frequency signal in receiving analog circuits are disclosed. With the key innovative circuits and methods for signal peak alignment, the disclosed circuits and methods achieve fast settling without significant attenuation of the input signal. Peak aligning circuits and methods can be implemented along with conventional RC AC coupling circuits. In applying the aligning circuits and methods to differential signal pair, DC offsets can be easily removed.

Circuits and methods for fast-settling signal alignment and DC offset removal

In a spread spectrum system, methods and despreader architectures for despreading the received spreaded codes with the use of a single correlator and a single correlation code is provided. Before despreading the incoming received spreaded codes, a single correlation code is generated using a symbol from a set of symbols that has been mapped into a set of differential encoded PN codes. Despreading output samples for each received spreaded code are obtained by correlating the received spreaded code with this single correlation code. Correlation is accomplished by multiplying each received sample of the received spreaded codes with the correlation code samples and accumulating the products of this multiplication. After correlation, the index for the maximum or minimum peak of the despreading output samples for each code is identified. This index can then be mapped into a symbol corresponding to the transmitted information. Corresponding despreader architectures comprise of a number of taps attached to a series of shift registers. Received samples of each received spreaded codes are inputted into the shift registers. The despreader architectures accumulates the products of multiplication of the value of the shift register with a predetermined value associated with each tap to produce the despreading output samples of a received spreaded code. It identifies the despreading output index producing the maximum of the absolute value of the despreading output and maps said index into a symbol corresponding to the transmitted information.

Chip-to-symbol receiver despreader architectures and methods for despreading spread spectrum signals

The present invention provides methods and apparatuses for an amplifier circuit for amplifying an input signal. An amplifier circuit for amplifying an input signal comprises an amplifying transistor circuit having a power transistor and a dc bias circuit having a plurality of current mirror circuits and a discharge transistor wherein the discharge transistor and the power transistor form a combined current mirror circuit to control quiescent current in the power transistor.

RF amplifier with a bias boosting scheme

The present invention provides methods and apparatuses for a polyphase filter, comprising: a first and second cascoded differential amplifiers configured to receive a first and second differential signals, the first cascoded differential amplifier having a first resistor coupled between current legs of the first cascoded differential amplifier and the second cascoded differential amplifier having a first capacitor coupled between current legs of the second cascoded differential amplifier; and a third and fourth cascoded differential amplifiers configured to receive said first and said second differential signals, the third cascoded differential amplifier having a second resistor coupled between current legs of the third cascoded differential amplifier and the fourth cascoded differential amplifier having a second capacitor coupled between current legs of the fourth cascoded differential amplifier; wherein the first and second cascoded differential amplifiers are configured to provide a first differential output in response to the first and second differential signals and the third and fourth cascoded differential amplifiers are configured to provide a second differential output in response to the first and second differential signals.

Growing community of inventors

Fremont, CA, United States of America

Chieh-Yuan Chao