Supermem, Inc.

Globalfoundries Inc.

Chieh-yu Lin

Yu Lu

Dongbing Shao

James A Culp

Richard Stewart

Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Error correcting memory systems

Memories, memory controllers, and computing systems and their methods of operation are disclosed. In some embodiments, a method of accessing a memory includes accessing a first bit line corresponding to a sense amplifier and accessing a second bit line corresponding to the sense amplifier. In some embodiments, a memory controller includes a second memory configured to store data of a second data type. In some embodiments, a method includes operating a memory in a second mode in response to receiving an input to change the operation of the memory from a first mode to the second mode.

Bit line sensing circuit comprising a sample and hold circuit

Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.

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San Diego, CA, United States of America

Chieh-yu Lin