Qualcomm Incorporated

Marvell International Limited

Chieh-Yu Hsieh

Dinesh Jagannath Alladi

Yan Wang

Seyed Arash Mirhaj

Yuhua Guo

Hossein Zarei

Lei Sun

Elias Dagher

Anand Meruva

Xiaopeng Zhong

ChienChung Yang

Yongjian Tang

Ji Ma

A sigma-delta analog-to-digital converter is provided that includes an initial continuous-time integration stage having a variable input resistor and an integration capacitor. A switched-capacitor circuit charges and discharges a replica capacitor to a reference voltage to generate a bias current. A SAR-based tuning circuit includes a variable tuning resistor that generates a tuning voltage while conducting a mirrored version of the bias current. A resistance of the variable input resistor is adjusted responsive to a tuning code from the SAR-based tuning circuit.

Analog-to-digital converter having time-constant tuning with pulse-width-based reference current and resistance searching

Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.

Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC)

Multi-channel receiver circuits implemented with time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits and methods for operating such receiver circuits are disclosed. One example receiver circuit generally includes a first multiplexer having a plurality of inputs coupled to a plurality of in-phase (I) receive paths associated with different channels of the receiver circuit, a first SAR ADC circuit having an input coupled to an output of the first multiplexer, a second multiplexer having a plurality of inputs coupled to a plurality of quadrature (Q) receive paths associated with the different channels of the receiver circuit, and a second SAR ADC circuit having an input coupled to an output of the second multiplexer.

Time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits for multi-channel receivers

A method and an apparatus for splitting a switched capacitor integrator of a delta-sigma modulator are provided. The apparatus configures a first integrator and a second integrator to be coupled in parallel to each other, switches between a first mode and a second mode, enables the first integrator to operate on an input signal to generate an output signal in the first mode, and enables the first integrator and the second integrator to cooperatively operate on the input signal in the second mode, wherein in the second mode, the apparatus generates a first output via the first integrator, generates a second output via the second integrator, and converges the first output with the second output to generate the output signal.

Multi-mode discrete-time delta-sigma modulator power optimization using split-integrator scheme

An analog-to-digital converter (ADC) and a receiver that includes the ADC is disclosed. The ADC includes a first filter configured to receive a signal in an I-signal path of the receiver and a second filter configured to receive a signal in a Q-signal path of the receiver. The ADC further includes a quantizer alternatingly in connection with the first and second filters, and at least one DAC alternatingly in connection with the first and second filters. Switches in the ADC are configured to alternate connection between an input of the quantizer and outputs of the first and second filters, and are also configured to alternate connection between an output of the at least one DAC and inputs of the first and second filters.

Compact high-speed analog-to-digital converter for both I and Q analog to digital conversion

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Irvine, CA, United States of America

Chieh-Yu Hsieh