Taiwan Semiconductor Manufacturing Comp. Ltd.

Chieh-Yi Shen

Ya-Lien Lee

Chia-Pang Kuo

Yu-Ming Lin

Chung-Te Lin

Meng-Han Lin

Feng-Cheng Yang

Han-Jong Chia

Ming-Hsi Yeh

Sheng-Chen Wang

Kuo-Bin Huang

Feng-Ching Chu

Chieh-Fang Chen

Meng-Hsien Li

Chih-Hsuan Cheng

Li-min Chen

Ying-Chuen Wang

A method for forming a semiconductor memory structure is provided. The method includes forming a stack over a substrate, and the stack includes first dielectric layers and second dielectric layers vertically alternately arranged. The method also includes forming first dielectric pillars through the stack, and etching the stack to form first trenches. Sidewalls of the first dielectric pillars are exposed from the first trenches. The method also includes removing the first dielectric pillars to form through holes, removing the second dielectric layers of the stack to form gaps between the first dielectric layers, and forming first conductive lines in the gaps.

Method for forming a 3-D semiconductor memory structure comprising horizontal and vertical conductive lines

A method of forming an integrated circuit structure includes forming an etch stop layer over a conductive feature, forming a dielectric layer over the etch stop layer, forming an opening in the dielectric layer to reveal the etch stop layer, and etching the etch stop layer through the opening using an etchant comprising an inhibitor. An inhibitor film comprising the inhibitor is formed on the conductive feature. The method further includes depositing a conductive barrier layer extending into the opening, performing a treatment to remove the inhibitor film after the conductive barrier layer is deposited, and depositing a conductive material to fill a remaining portion of the opening.

Selective deposition of metal barrier in damascene processes

A wet etching chemistry to selectively remove a polymer residue on an opening embedded in a low-k dielectric layer and an underlying stop layer in a process of forming an interconnect structure is provided. The wet etching chemistry includes: two type of organic solvents, wherein a concentration of the two type of organic solvents is greater than or equal to 70%; an Alkali source amine, at least comprising a tertiary amine; an inhibitor; and water. In some embodiment, the wet etching chemistry is free of a peroxide to avoid damage to the WdC hard mask.

Wet etching chemistry and method of forming semiconductor device using the same

Selective deposition of metal barrier in damascene processes and the structures formed thereof

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Taipei, Taiwan

Chieh-Yi Shen