Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Apple Inc.

National Taiwan University

Academia Sinica

Hannstar Display Corporation

Chieh-Wei Chen

Chun-Neng Lin

Jian-Jou Lian

Ming-Hsi Yeh

Tzu-Ang Chiang

Ting-Kuo Chang

Chun-Liang Lin

Po-Yuan Wang

Jenn-Jia Su

Tzu Ang Chiang

Paul Stephen Drzaic

Te-Wei Chan

Chung-Yi Chiu

Cheng-Han Tsao

Chen-Chi Lin

Ting-Yi Cho

Cheng-Ho Yu

Chia-Yu Lee

Hung-Lung Hou

Warren S Rieutort-Louis

Yen-Heng Huang

Yifan Zhang

Chung-Kai Chen

Chung-Chun Lee

Chin-An Tseng

Meng-Ting Lee

Shih Chang Chang

Tsung-Ting Tsai

Jean-Pierre Simon Guillou

Wen-Hao Hsu

Young Bae Park

Hao Chen

Tien-Lun Ting

ByoungSuk Kim

Yi Huang

Chung-Chih Wu

Meng-Huan Ho

Wei-Kai Huang

Tae-Wook Koh

Donghee Nam

Chih-Haw Wang

Ping-Yen Chou

Hitoshi Yamamoto

Kung-Ching Chu

Mathew K Mathai

Brett W Degner

John Z Zhong

Dinesh C Mathew

Wei Hsin Yao

Chin-Wei Lin

Chaohao Wang

Hung Sheng Lin

Hyunwoo Nho

Yafei Bi

Kingsuk Brahma

Abbas Jamshidi Roudbari

Vasudha Gupta

Shinya Ono

Marc Albrecht

Lei Yuan

Qing Li

Jia-Shyong Cheng

Shengkui Gao

Shyuan Yang

Chung-Chia Chen

Kuo-Hua Sung

Jae Won Choi

Koorosh Aflatooni

Injae Hwang

Chia-Hui Pai

Chao-Yuan Chen

Pierre-Yves Emelie

Sean C Chang

Yuchi Che

Bhadrinarayana Lalgudi Visweswaran

Myung-Je Cho

Yuan-Chun Wu

Chia-Yu Chen

Yue Jack Chu

Silvio Grespan

Yu-Shih Wang

Graeme M Williams

Ken-Tsung Wong

Yao-An Mo

Shi-Hao Li

Jung Yen Huang

Doh-Hyoung Lee

Yi-Pai Huang

Chun-Hsiang Fang

Mohammad Hajirostam

Niva A Ran

Sang Ha Kim

Ricardo A Peterson

Anshi Liang

Po-Chun Yeh

Jiun-Jye Chang

Salman Kabir

Bo-Ren Wang

A method of fabricating a semiconductor device includes forming at least one fin on a substrate, a plurality of dummy gates over the at least one fin, and a sidewall spacer on the dummy gates. Source and drain regions are epitaxially formed contacting the at least one fin and laterally adjacent the dummy gates, where forming the source and drain regions leaves a void below the source and drain regions and adjacent the dummy gates. The dummy gates are replaced with active gates, each having a gate dielectric on the sidewall spacer and a gate electrode on the gate dielectric. A patterned layer is formed exposing a selected active gate of the active gates. A first etch is performed to remove exposed portions of the gate electrode of the selected active gate. A second etch is performed, after the first etch, to remove exposed portions of a gate dielectric of the selected active gate.

Semiconductor devices and methods of manufacturing thereof

A method of forming a semiconductor device includes surrounding a dummy gate disposed over a fin with a dielectric material; forming a gate trench in the dielectric material by removing the dummy gate and by removing upper portions of a first gate spacer disposed along sidewalls of the dummy gate, the gate trench comprising a lower trench between remaining lower portions of the first gate spacer and comprising an upper trench above the lower trench; forming a gate dielectric layer, a work function layer and a glue layer successively in the gate trench; removing the glue layer and the work function layer from the upper trench; filling the gate trench with a gate electrode material after the removing; and removing the gate electrode material from the upper trench, remaining portions of the gate electrode material forming a gate electrode.

Fin Field-Effect Transistor device and method of forming the same

An organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. Voltage may be applied to the anode of each pixel to control the magnitude of emitted light. The conductivity of the OLED layers may allow leakage current to pass between neighboring anodes in the display. To reduce leakage current and the accompanying cross-talk, the display may include active and/or passive leakage-mitigating structures. The passive leakage-mitigating structures may have an undercut that causes discontinuities in the overlying OLED layers. Active leakage-mitigating structures may include a conductive layer (e.g., a conductive ring) that drains leakage current to ground. Alternatively, the active leakage-mitigating structures may include a gate electrode modulator with a variable voltage that stops the current flow laterally.

Organic light-emitting diode display with passive leakage-reducing structures

A method for manufacturing a semiconductor device includes: forming a patterned dielectric layer over a substrate, the patterned dielectric layer including an interconnect opening having a sidewall surface and a bottom surface; and forming a doped film by an opening-adjustment process, the doped film being disposed on the patterned dielectric layer and extending into the interconnect opening to cover an upper portion of the sidewall surface, so as to adjust a profile of the interconnect opening.

Method for improving profile of interconnect structure

A semiconductor device includes a gate electrode over a channel region of a semiconductor fin, first spacers over the semiconductor fin, and second spacers over the semiconductor fin. A lower portion of the gate electrode is between the first spacers. An upper portion of the gate electrode is above the first spacers. The second spacers are adjacent the first spacers opposite the gate electrode. The upper portion of the gate electrode is between the second spacers.

Fin field-effect transistor device and method of forming the same

A lenticular display may be formed with convex curvature. The lenticular display may have a lenticular lens film with lenticular lenses that extend across the length of the display. The lenticular lenses may be configured to enable stereoscopic viewing of the display. To enable more curvature in the display while ensuring satisfactory stereoscopic display performance, the display may have stereoscopic zones and non-stereoscopic zones. A central stereoscopic zone may be interposed between first and second non-stereoscopic zones. The non-stereoscopic zones may have more curvature than the stereoscopic zone. To prevent crosstalk within the lenticular display, a louver film may be incorporated into the display. The pixel array may have a diagonal layout and may be covered by vertically oriented lenticular lenses.

Pixel arrangements for electronic device displays

In a wet etching process to pattern a metal layer such as a p-metal work function layer over a dielectric layer such as a high-k gate dielectric layer, a selectivity of the wet etching solution between the metal layer and the dielectric layer is increased utilizing an inhibitor. The inhibitor includes such inhibitors as a phosphoric acid, a carboxylic acid, an amino acid, or a hydroxyl group.

Semiconductor device and method of manufacture

An electronic device includes a display and a sensor underneath the display. The display has a full pixel density region and a reduced pixel density region. Compared to pixels in the full pixel density region, pixels in the reduced pixel density region can be controlled using overdriven power supply voltages, overdriven scan control signals, different initialization and reset voltages, and can include capacitors and transistors with different physical and electrical characteristics. Gate drivers provide scan signals to pixels in the full pixel density region, whereas overdrive buffers provide overdrive scan signals to pixels in the reduced pixel density region. The pixels in the full pixel density region and the pixels in the reduced pixel density region can be controlled using different black level or gamma settings for each color channel and can be adjusted physically to match luminance, color, as well as to mitigate differences in temperature and aging impact.

Displays having reduced pixel density region with localized tuning

A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Method of forming semiconductor device

A semiconductor device includes a semiconductor fin. The semiconductor device includes a metal gate disposed over the semiconductor fin. The semiconductor device includes a gate dielectric layer disposed between the semiconductor fin and the metal gate. The semiconductor device includes first spacers sandwiching the metal gate. The first spacers have a first top surface and the gate dielectric layer has a second top surface, and the first top surface and a first portion of the second top surface are coplanar with each other. The semiconductor device includes second spacers further sandwiching the first spacers. The second spacers have a third top surface above the first top surface and the second top surface. The semiconductor device includes a gate electrode disposed over the metal gate.

Fin field-effect transistor and method of forming the same

A semiconductor device includes a semiconductor fin. The semiconductor device includes first spacers over the semiconductor fin. The semiconductor device includes second spacers over the semiconductor fin. The second spacers vertically extend farther from the semiconductor fin than the first spacers. The semiconductor device includes a metal gate over the semiconductor fin, the metal gate is sandwiched by the first spacers. The metal gate includes a glue layer that contains tantalum nitride.

A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.

Patterning method and structures resulting therefrom

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Taichung, Taiwan

Chieh-Wei Chen