Siliconware Precision Industries Co., Ltd.

Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Toalux Electric Corp.

Chieh-Lung Lai

Chang-Lun Lu

Jian-Shian Lin

Mao-Hua Yeh

Shih-Liang Peng

Hung-Yuan Li

Lu-Yi Chen

Hsiu-Jen Lin

Hsien-Wen Chen

Chun-Hung Lu

Shih-Ching Chen

Cheng-Yi Chen

Hsien-Wei Chen

Shin-Puu Jeng

Shih-Chang Chen

Meng-Liang Lin

Tung-Chuan Wu

Hong-Da Chang

Chang-Yueh Chan

Yi-Ping Huang

Lei-Yi Chen

Jen-Hui Tsai

Weng-Jung Lu

Yi-Ting Sun

Hsiu-Chen Hsu

Yu-Chuan Chen

Shau-Yi Chen

Jia-Wei Pan

Chih-Sheng Hsu

Ya-Chun Tu

Jian-Chiuan Wang

A semiconductor device includes: a die having die connectors at a front side of the die; a molding material around the die; and a redistribution structure, where the die connectors of the die are attached to a first side of the redistribution structure, where the redistribution structure includes: a dielectric layer; a conductive line extending along a first surface of the dielectric layer facing the die; and a warpage tuning layer contacting and extending along a first surface of the conductive line facing the die, where a first coefficient of thermal expansion (CTE) of the conductive line is smaller than a second CTE of the warpage tuning layer.

Redistribution structure with warpage tuning layer

The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

Method for manufacturing electronic package

Electronic package and method for manufacturing the same

An electronic package is provided, which includes: a circuit structure having opposite first and second surfaces; a metal layer formed on the first surface of the circuit structure; an electronic element disposed on the metal layer; an encapsulant encapsulating the electronic element; a plurality of conductive posts disposed on the second surface of the circuit structure; and an insulating layer encapsulating the conductive posts. The conductive posts of various sizes can be fabricated according to different aspect ratio requirements so as to make end products lighter, thinner, shorter and smaller. The disclosure further provides a method for fabricating the electronic package.

Method for fabricating electronic package

A package structure includes a dielectric layer having opposing first and second surfaces, a wiring layer formed on the first surface and having a plurality of conducive vias that penetrate the dielectric layer, an electronic component disposed on the first surface of the dielectric layer and electrically connected to the wiring layer, an encapsulant encapsulating the electronic component, and a packaging substrate disposed on the second surface and electrically connected to the conductive vias. With the dielectric layer in replacement of a conventional silicon board and the wiring layer as a signal transmission medium between the electronic component and the packaging substrate, the package structure does not need through-silicon vias. Therefore, the package structure has a simple fabrication process and a low fabrication cost. The present invention further provides a method of fabricating the package structure.

Method of fabricating packaging structure

Electronic package and method for fabricating the same

A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided.

Electronic package and semiconductor substrate

A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the electronic package

A substrate structure is provided, which includes a substrate body having a plurality of conductive pads, and a plurality of first conductive bumps and a plurality of second conductive bumps disposed on the conductive pads. Each of the second conductive bumps is less in width than each of the first conductive bumps, and is of a height with respect to the substrate body greater than a height of each of the first conductive bumps with respect to the substrate body. Therefore, the height difference between the first pre-solder layer and the second pre-solder layer after a reflow process can be compensated, and the first conductive bumps and the second conductive bumps thus have a uniform height.

Substrate structure with first and second conductive bumps having different widths

A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Package structure and method for fabricating the same

An LED package structure includes: a carrier; at least a first protruding portion and a plurality of electrical contacts formed on the carrier; a plurality of LED chips disposed on the first protruding portion and on the carrier in a region free from the first protruding portion, respectively; a plurality of bonding wires electrically connecting the LED chips and the electrical contacts; and a phosphor covering the LED chips, the electrical contacts and the bonding wires. The LED chips are disposed at different heights so as to allow the portions of the phosphor on the LED chips to have different thicknesses and thus generate light with different color temperatures.

LED package structure and fabrication method thereof

A die-bonding method is suitable for die-bonding a LED chip having a first metal thin-film layer to a substrate. The method includes forming a second metal thin film layer on a surface of the substrate; forming a die-bonding material layer on the second metal thin film layer; placing the LED chip on the die-bonding material layer with the first metal thin film layer contacting the die-bonding material layer; heating the die-bonding material layer at a liquid -solid reaction temperature for a pre-curing time, so as to form a first intermetallic layer and a second intermetallic layer; and heating the die-bonding material layer at a solid-solid reaction temperature for a curing time for performing a solid-solid reaction. The liquid-solid reaction temperature and the solid-solid reaction temperature are both lower than 110&#xb0; C., and a melting point of the first and second intermetallic layers after the solid-solid reaction is higher than 200&#xb0; C.

Die-bonding method of LED chip and LED manufactured by the same

A light-emitting diode (LED) module and an LED packaging method. As the LED module is packaged under the consideration of candela distribution, each of the lead frames of the LED chips packaged in the LED module is bended for tilting the LED chips by different angles to exhibit various lighting effects. Meanwhile, in the LED packaging method, a plurality of LED chips can be loaded on board rapidly and aligned by one operation to result in less deviation in the candela distribution curve.

LED module and packaging method thereof

A light source device is disclosed, which involves forming a plurality of carrier planes on a substrate with at least one of the carrier planes forming an angle relative to the substrate, and respectively mounting LEDs on the carrier planes and electrically connecting the LEDs with the carrier planes so as to obtain a preferred light distribution effect, thereby eliminating the need of additional light control element in the prior art and enhancing light emitting efficiency of the light source device.

Light source device

An improved lamp fixture with anti-glare function is disclosed, which comprises: a lamp; a light source; and a light-control unit, composed of a semi-Fresnel microstructure and a light-control microstructure; wherein the light source and the light-control unit are mounted on the lamp; and the semi-Fresnel microstructure is used for diffusing/collimating light of the light source while the light-control microstructure is used for controlling the resulting lighting angle. With the aforesaid lamp fixture, not only glare can be prevented, but also uniformity of the lamp fixture is improved.

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Taichung, Taiwan

Chieh-Lung Lai