Taiwan Semiconductor Manufacturing Comp. Ltd.

Chieh-Han Wu

Chung-Ju Lee

Cheng-Hsiung Tsai

Hwei-Jay Chu

Shau-Lin Shue

Tien-I Bao

Chih Wei Lu

Ru-Gun Liu

Jeng-Horng Chen

Shinn-Sheng Yu

Ming-Feng Shieh

Chih-Tsung Shih

Hsin-Chieh Yao

Tsung-Min Huang

Ming-Han Lee

Shin-Yi Yang

Tsung-Yu Chen

Chien-Hua Huang

Chih-Wei Lu

Yu-Fu Lin

Tzu-Hui Wei

An-Dih Yu

An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature having a first thickness, a first dielectric material disposed adjacent the first conductive feature, and the first dielectric material has a second thickness greater than the first thickness. The structure further includes a second conductive feature disposed adjacent the first dielectric material, a first etch stop layer disposed on the first conductive feature, a second etch stop layer disposed on the first dielectric material, and a second dielectric material disposed on the first etch stop layer and the second etch stop layer. The second dielectric material is in contact with the first dielectric material.

Semiconductor device structure and methods of forming the same

Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Self-aligned via for interconnect structure

A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.

Semiconductor structure and method for forming the same

Interconnect structure having a barrier layer along the sidewall of self-aligned via structures

A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

Semiconductor structure having air gaps and method for manufacturing the same

Method of fabricating self-aligned via structures

A method for forming a semiconductor structure includes forming a first cap layer over a metal layer. The method also includes patterning the metal layer and the first cap layer to form openings exposing the gate structure, and forming a first dielectric layer in the openings, and patterning the first cap layer to form a via cap plug over the metal layer. The method also includes forming a second dielectric layer over the via cap plug and the metal layer, and forming a trench in the second dielectric material to expose the via cap plug. The method also includes removing the via cap plug to enlarge the trench and filling the trench with a conductive material.

Self-aligned via structures with barrier layers

A method of forming a target pattern includes forming a plurality of lines over a substrate with a first mask and forming a first spacer layer over the substrate, over the plurality of lines, and onto sidewalls of the plurality of lines. The plurality of lines is removed, thereby providing a patterned first spacer layer over the substrate. The method further includes forming a second spacer layer over the substrate, over the patterned first spacer layer, and onto sidewalls of the patterned first spacer layer, and forming a patterned material layer over the second spacer layer with a second mask. Whereby, the patterned material layer and the second spacer layer collectively define a plurality of trenches.

Semiconductor device including a target integrated circuit pattern

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A substrate having a dielectric layer over it is provided. A block co-polymer (BCP) layer is deposited over the dielectric layer. The BCP layer is then annealed to form a first polymer nanostructures surrounded by a second polymer nanostructures over the dielectric layer. The second polymer nanostructure is selectively etched using the first polymer nanostructure as an etch mask to form a nano-block. The dielectric layer is selectively etched using the nano-block as an etch mask to form a nano-trench. The nano-trenched is sealed to form a nano-air-gap.

Semiconductor integrated circuit with nano gap

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first layer is deposited over a substrate. A plurality of mandrels is formed over the first layer. Guiding-spacers are formed along sidewalls of the mandrels. Then the mandrels are removed. A neutral layer (NL) and a block copolymer (BCP) layer are deposited over the first layer and the guiding-spacers. A anneal is applied to the BCP layer to form a first polymer nanostructure between the guiding-spacers and being surrounded by a second polymer nanostructure. The first polymer nanostructures locate at a same distance from the first layer. Polymer nano-blocks are formed by selectively etching the second polymer nanostructure and the NL. By using the polymer nano-blocks and the guiding spacer as etch masks, the first layer is etched to form openings. The substrate is etched through the openings to form substrate trench and substrate fin.

Method of fabricating a semiconductor integrated circuit using a directed self-assembly block copolymer

Method of spacer patterning to form a target integrated circuit pattern

A method includes forming a resist over a substrate, resulting in a layer of resist scum between the resist and the substrate. The method further includes forming trenches in the resist, wherein at least a portion of the layer of resist scum remains between the trenches and the substrate. The method further includes forming a first material layer in the trenches, wherein the first material layer has a higher etch resistance than the resist in an etching process. The method further includes performing the etching process to the first material layer, the resist, and the layer of resist scum, thereby forming a patterned first material layer over a patterned layer of resist scum over the substrate.

Method for integrated circuit patterning

A method includes forming a patterned mask layer over a conductive layer; forming a first dielectric layer over the patterned mask layer and the conductive layer; selectively etching the first dielectric layer, thereby exposing an upper surface of the patterned mask layer, wherein the upper surface of the first dielectric layer is lower than a top surface of the patterned mask layer; removing the patterned mask layer; and selectively etching the conductive layer to form a conductive feature having a tapered profile.

Growing community of inventors

Kaohsiung, Taiwan

Chieh-Han Wu