Macronix International Co., Ltd.

International Business Machines Corporation

Qimonda North America Corporation

Chieh Fang Chen

Chung H Lam

Hsiang-Lan Lung

Matthew Joseph Breitwisch

ChiaHua Ho

Hsiang Lan Lung

Shih Hung Chen

Thomas Happ

Alejandro Gabriel Schrott

Yen-Hao Shih

Eric Andrew Joseph

Jan Boris Philipp

Geoffrey W Burr

Yi-Chou Chen

Yi Chou Chen

A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.

Method for manufacturing a phase change memory device with pillar bottom electrode

A protective layer is deposited on a chalcogenide layer and a patterned photoresist layer is formed on the protective layer. The patterned photoresist layer and the protective layer are etched to form openings therethrough to the chalcogenide layer to create etched photoresist and etched protective layers. The etched photoresist layer is removed leaving at least a portion of the etched protective layer. The chalcogenide layer is etched through the openings in the etched protective layer.

Chalcogenide layer etching method

A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

Fill-in etching free pore device

Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.

Phase change device having two or more substantial amorphous regions in high resistance state

A method of manufacturing for providing a narrow line, such as a phase change bridge, on a substrate having a top surface, includes first forming a layer of first material on the substrate. Then, a layer of a pattern material is applied on the layer of first material, and a pattern is defined. The pattern includes a ledge having a sidewall extending substantially to the layer of first material. A sidewall etch mask is formed on the ledge, and used to define a line of the first material on the substrate having a width substantially determined by the width of the sidewall etch mask.

Method for manufacturing a narrow structure on an integrated circuit

A memory cell device, including a memory material element switchable between electrical property states by the application of energy, includes depositing an electrical conductor layer, depositing dielectric material layers and etching to create a first electrode and voids. A memory material is applied into a void to create a memory material element in contact with the first electrode. A second electrode is created to contact the memory material element.

Method for making memory cell device

Nonvolatile memory cells with programmable resistive memory elements, such as chalcogenide material elements, undergo a refresh operation. A refresh operation includes a hot signal and a cold signal, where the hot signal has higher power than a reset signal, and a cold signal has a longer duration than a set signal.

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Panchiao, Taiwan

Chieh Fang Chen