Macronix International Co., Ltd.

International Business Machines Corporation

Qimonda North America Corporation

Chieh-Fang Chen

Hsiang-Lan Lung

Chung H Lam

Simone Raoux

Matthew Joseph Breitwisch

Ming-Hsiu Lee

Yen-Hao Shih

Alejandro Gabriel Schrott

Yi-Chou Chen

Huai-Yu Cheng

Shih-Hung Chen

Thomas Happ

Eric Andrew Joseph

Min Yang

Jan Boris Philipp

Yu-Wei Jiang

Michael F Lofaro

Ming-Hsiang Hsueh

Shih Hung Chen

Chia Hua Ho

Chao-I Wu

Yu Zhu

Teng-Hao Yeh

Chih-Wei Hu

Hsiang Lan Lung

Kuo-Pin Chang

Philip L Flaitz

Ming Hsiu Lee

Jia-Rong Chiou

Frieder Heinrich Baumann

Lee-Yin Lin

A semiconductor structure includes a substrate, conductive layers, dielectric layers, an isolation structure, a first memory structure, and a second memory structure. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The isolation structure is disposed on the substrate and through the conductive layers and the dielectric layers. Each of the first and second memory structures has a radius of curvature. The first and second memory structures penetrate through the conductive layers and the dielectric layers and are disposed on opposite sidewalls of the isolation structure. Each of the first and second memory structures includes protecting structures and a memory structure layer including a memory storage layer. The protecting structures are disposed at two ends of the memory storage layer, and an etching selectivity to the protecting structures is different from an etching selectivity to the memory storage layer.

Semiconductor structure and manufacturing method thereof

A 3D memory device includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a memory layer and a channel layer. The insulating layers are alternately stacked with the conductive layers on the substrate to form a multi-layers stacking structure, wherein the multi-layers stacking structure has at least one trench penetrating through the insulating layers and the conductive layers. The memory layer covers on the multi-layers stacking structure and at least extends onto a sidewall of the trench. The cannel layer covers on the memory layer and includes an upper portion adjacent to an opening of the trench, a lower portion adjacent to a bottom of the trench and a string portion disposed on the sidewall, wherein the string portion connects the upper portion with the lower portion and has a doping concentration substantially lower than that of the upper portion and lower portion.

Three dimensional memory device and method for fabricating the same

A device, such as an integrated circuit including memory, includes an array of memory cells on a substrate. A row/column line, such as a local word line or local bit line, is disposed in the array. The row/column line includes a pass transistor structure comprising a semiconductor strip in a first patterned layer over the substrate. The semiconductor strip includes a semiconductor channel body, a contact region on one side of the semiconductor channel body, and an extension on another side of the semiconductor channel body, which reaches into the memory cells in the array. A select line in a second patterned layer crossing the semiconductor channel body is provided. The pass transistor structure can be implemented in a fanout structure for row/column lines in the array.

Array fanout pass transistor structure

A memory cell described herein includes a memory element comprising programmable resistance memory material overlying a conductive contact. An insulator element includes a pipe shaped portion extending from the conductive contact into the memory element, the pipe shaped portion having proximal and distal ends and an inside surface defining an interior, the proximal end adjacent the conductive contact. A bottom electrode contacts the conductive contact and extends upwardly within the interior from the proximal end to the distal end, the bottom electrode having a top surface contacting the memory element adjacent the distal end at a first contact surface. A top electrode is separated from the distal end of the pipe shaped portion by the memory element and contacts the memory element at a second contact surface, the second contact surface having a surface area greater than that of the first contact surface.

Phase change memory cell structure

A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

Composite target sputtering for forming doped phase change materials

An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode.

Method to selectively grow phase change material inside a via hole

A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.

Memory device and method of operating the same

A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

Method for forming a self-aligned bit line for PCRAM and self-aligned etch back process

A phase change memory cell with a single element phase change thin film layer; and a first electrode and a second electrode coupled to the single element phase change thin film layer. A current flows from the first electrode to the single element phase change thin film layer, and through to the second electrode. The single element phase change thin film layer includes a single element phase change material. The single element phase change thin film layer can be less than 5 nanometers thick. The temperature of crystallization of the single element phase change material can be controlled by its thickness. In one embodiment, the single element phase change thin film layer is configured to be amorphous at room temperature (25 degrees Celsius). In one embodiment, the single element phase change thin film layer is comprised of Antimony (Sb).

Phase change memory random access device using single-element phase change material

A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of 'non-constant' concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

Phase change memory having one or more non-constant doping profiles

A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

Dielectric mesh isolated phase change structure for phase change memory

Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode, a top electrode overlying the bottom electrode, a via having a sidewall extending from a bottom electrode to a top electrode, and a memory element electrically coupling the bottom electrode to the top electrode. The memory element has an outer surface contacting a dielectric sidewall spacer that is on the sidewall of the via, and comprises a stem portion on the bottom electrode and a cup portion on the stem portion. A fill material is within an interior defined by an inner surface of the cup portion of the memory element.

Growing community of inventors

Banciao, Taiwan

Chieh-Fang Chen