Xilinx, Inc.

Chidamber R Kulkarni

Gordon John Brebner

Philip Bryn James-Roxby

Eric R Keller

Stephen M Trimberger

Arifur Rahman

Michael Alan Baxter

Schuyler E Shimanek

Graham F Schelle

Wayne Edward Wennekamp

Gary R Lawman

Kerry M Pierce

James A Walstrum, Jr

Henry E Styles

Thomas H Strader

Mikhail A Wolf

Christopher E Neely

Joe E Leyba

Schulyer E Shimanek

Steven E Mcneil

Adam Elklns

Christoforos Kachris

A multi-port memory controller (MPMC) can be parameterized to selectively connect to different memory configurations. In particular, a programmable device that is combined with a DRAM in a die-stacked distributed memory in a single chip is provided with the programmable device forming the MPMC. The programmable device is parameterized to form a memory controller that can either aggregate or segment memory controller components to control different DRAM memory banks either together or separately. The aggregation or segmentation of the memory devices can be configured dynamically during operation of the programmable device.

Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)

A memory controller implemented within a programmable integrated circuit can include a user interface having a command register and a plurality of data First-In-First-Out (FIFO) memories, wherein the command register can receive an address of a data FIFO memory of the plurality of data FIFO memories. A core controller coupled to the user interface can, responsive to an instruction from the user interface, generate control signals that initiate an operation within a memory device coupled to the core controller. A physical layer coupling with the core controller, the user interface, and the memory device can, responsive to a read operation of the memory device, store data received from the memory device within the selected data FIFO memory according to the address received in the command register.

Programmable memory controller

A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.

Generation of a specification of a network packet processor

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.

Method and apparatus for multithreading on a programmable logic device

A method of automatically generating multithreaded datapaths from a circuit description can include identifying a plurality of process threads from a circuit description, wherein each process thread comprises at least one function, and representing each of the plurality of process threads as an order of operations graph including nodes that correspond to functions and edges that indicate dependencies between the functions. The method also can include identifying at least one conditional edge from the order of operations graphs. An updated circuit description can be generated that specifies a multiplexer for each conditional edge.

Automatically generating multithreaded datapaths

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.

Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.

Method for message processing on a programmable logic device

Method and apparatus for managing memory logic is described. In one example, user logic, virtual port logic, and a processor are provided. The user logic is configured to provide allocation requests for the memory logic, access requests for the memory logic, and de-allocation requests for the memory logic. The virtual port logic is coupled to the user logic and the memory logic. The processor is coupled to the virtual port logic. The virtual port logic is configured to forward the allocation requests and de-allocation requests to the processor, and to process the access requests. The processor is configured to allocate space in the memory logic in response to the allocation requests and de-allocate space in the memory logic in response to the de-allocation requests.

Method and apparatus for memory management in an integrated circuit

A method and system for concurrent data processing, and an integrated circuit having programmable logic therefor, are described. A multi-threaded application is parsed into respective threads. Data value variables, data operators, data processing order of execution, and data result variables are identified from the threads. A code listing is generated associated with each of the threads for the data value variables, the data operators, the data processing order of execution, and the data result variables identified. Source and destination address information is associated with the data value variables and the data result variables. The source and destination address information is ordered to preserve the data processing order of execution. A configuration bitstream is generated for instantiating thread-specific processors in programmable logic, the thread-specific processors associated with the threads each having at least a portion of the data operators.

Micro-coded processors for concurrent processing in a programmable logic device

A method and apparatus that uses device defects as an identifier. Data is written to memory of an integrated circuit. Defects are identified based upon the writing of the data. An identifier for the IC is then derived using the identification of the defects.

Method and apparatus using device defects as an identifier

Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system () includes a set of n processing elements () for processing messages, where n is an integer greater than zero. A set of m memories () is provided for storing the messages, where m is an integer greater than zero. Multiplexing logic () is provided for coupling each of the processing elements to each of the memories. Control logic () is provided for driving the multiplexing logic to provide access to each of the memories among the processing elements in accordance with a gated module-n schedule.

Memory apparatus for a message processing system and method of providing same

Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.

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Santa Clara, CA, United States of America

Chidamber R Kulkarni