Globalfoundries Inc.

Chidam Kallingal

Norman Chen

Yuyang Sun

Ayman Hamouda

Chang A Wang

Methods for retargeting a circuit design layout for a multiple patterning lithography process and for fabricating a semiconductor device are provided. In an exemplary embodiment, a computer-executed method for retargeting a circuit design layout for a multiple patterning lithography process is provided. The method includes decomposing a circuit design layout file to produce decomposed layout files in a computer. Each decomposed layout file is associated with a respective mask for use in the multiple patterning lithography process. The method includes preparing retargeted layout files in the computer by retargeting selected decomposed layout files based on photolithography limitations specific to each selected decomposed layout file to produce retargeted layout files. Also, the method includes determining in the computer that a combination of layout files includes a spacing conflict. The method further includes resolving the spacing conflict in the computer by modifying the layout file or layout files causing the spacing conflict.

Methods for retargeting circuit design layouts and for fabricating semiconductor devices using retargeted layouts

A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Retargeting semiconductor device shapes for multiple patterning processes

Embodiments of the invention provide approaches for optimizing illumination and polarization for advanced optical lithography. Specifically, an illumination pupil plane of an illumination source is bisected into a plurality of elements. Preferred elements of the illumination pupil plane are selected for a set of integrated circuit (IC) design features. An imaging performance of the set of IC design features for the preferred elements is evaluated at different polarization states to determine an optimal illumination and polarization condition for each IC design feature. Imaging performance of the combined IC design features, evaluated at various optimal illumination and polarization outcomes synthesized at different intensity ratios, is reviewed against a set of design tolerance requirements to finalize optical illumination and polarization conditions for the entire IC design. An optimal illumination and polarization solution is identified for an off-contact pattern with a plurality of sub-resolution assisted features connecting line-line-end portions of main mask features.

Use of polarization and composite illumination source for advanced optical lithography

Methods for fabricating a semiconductor device and a lithographic mask of use in that method are provided for. The lithographic mask comprises an optically transparent substrate, an attPSM pattern overlying the optically transparent substrate, and a phase shifted optically transparent portion adjacent to and aligned with an edge of the attPSM pattern.

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Poughkeepsie, NY, United States of America

Chidam Kallingal