Hkc Corporation Limited

Beihai Hkc Optoelectronics Technology Co., Ltd.

Chiayang Cheng

Chongwei Tang

Wei Li

Provided are a circuit, a method of driving the panel, and a display device. The driving circuit includes a plurality of scanning lines, a plurality of clock signal connecting lines, a time controller and a multiple shift register unit. The input end of the shift register unit is correspondingly connected to the other end of the clock signal connecting line to receive clock signals of the time controller, and the output ends of the shift register units are connected with the scanning lines in one-to-one correspondence; Starting from the first shift register unit, the adjacent two shift register units are taken as a shift register group, and the clock signals sent by the time controller to the two shift register units in the same group via the clock signal connecting line have the same waveform.

Circuit, method of driving panel, and display device

Disclosed are an array substrate drive circuit, a display module and a display device. The array substrate drive circuit includes: a signal driver configured for receiving a test signal, and generating a drive signal for driving a pixel array according to the test signal; and a signal isolator configured for dividing the drive signal into an even-numbered row drive signal and an odd-numbered row drive signal for driving the pixel array according to a preset control signal to drive the pixel array in rows. Since adjacent metal conductive layers will not output drive signals at the same time, even if the adjacent metal conductive layers are short-circuited, it can be detected during the test, thus improving the yield of the display panel.

Array substrate drive circuit, display module and display device

A gate drive circuit includes: N array substrate row drive circuits arranged in cascade, an Nth array substrate row drive circuit is configured for outputting an Nth gate drive signal in response to a signal input terminal receiving a gate drive signal output by an N&#x2212;1th array substrate row drive circuit to control Nth sub-pixels to charge; N auxiliary circuits, a timing signal input terminal is connected to an Nth timing control signal, a controlled terminal is connected to a pull-up control signal terminal of the N&#x2212;1th array substrate row drive circuit, and an output terminal is connected to a gate drive signal output terminal; and the Nth auxiliary circuit is configured for controlling the Nth sub-pixels to charge in a determination that the Nth timing control signal connected to the timing signal input terminal and an N&#x2212;1th pull-up control signal connected to the controlled terminal are both high level.

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Guangxi, China

Chiayang Cheng