Sgs-thomson Microelectronics Limited

Sgs-thomson Microelectronics S.r.l.

Chiara Zaccherini

Girish A Dixit

Robert O Miller

Che C Wei

A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact opening to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

Self-aligned contact formation

A process for forming implanted regions with lowered channelling risk on semiconductors, wherein the semiconductor devices include at least one layer of polycrystalline silicon which covers all isolation regions and active areas which are liable to a channelling phenomena and wherein the process includes masking the areas or regions to be implanted on the polycrystalline layer, implanting a first dopant species having a high atomic weight to amorphousize the polycrystalline silicon in any unmasked areas, removing the masking layer, and implanting a second dopant species over the entire semiconductor.

Process for forming implanted regions with lowered channeling risk on

A polycrystalline silicon layer is deposited and patterned to define a level of interconnect. Contact openings to lower conductive layers are then defined and patterned. A refractory metal such as tungsten is selectively deposited over the device, so that it adheres to the polycrystalline silicon in the interconnect leads and silicon of the lower conductive layer which is exposed in the contact openings. This provides a low resistance interconnect, and good, metal, contacts to underlying layers. Shared contacts between two or more polycrystalline silicon interconnect layers and in underlying conductive layers such as a substrate are easily formed using this technique.

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Milan, Italy

Chiara Zaccherini