Cisco Technology, Inc.

Chiara Piglione

Rong Pan

Hiroshi Suzuki

Frederick Juergens Baker

Preethi Natarajan

Valentina Alaria

Mythili Suryanarayana Prabhu

Flavio Giovanni Bonomi

Alon Shlomo Bernstein

Ming Zhang

Davide Bergamasco

Dipankar Bhatt Acharya

Guglielmo Marco Morandin

Vijaynarayanan Subramanian

Chien Fang

Bill Carroll VerSteeg

Michele Caramello

Guglielmo Morandin

In one implementation, an input queue switch provides latency fairness across multiple input ports and multiple output ports. In one embodiment, each input port maintains a virtual output queue for each associate output port. The virtual output queues across multiple inputs are aggregated for each specific output port. The sum of the lengths of the virtual output queues is compared to a threshold, and based on the comparison, feedback may be generated to control the operation of the input port for subsequent packets. The feedback may instruct the input port to stop buffering or drop packets destined for the output port with the sum of the lengths of the virtual output queues associated to the specific output port that exceeds the threshold. In another embodiment, each packet has an arrival timestamp, and a virtual output queue having the oldest timestamp is selected first to dequeue.

Output queue latency behavior for input queue based device

An example method for adapting Proportional Integral controller Enhanced (PIE) algorithm for varying network conditions is provided and includes estimating an average dequeue rate at which packets are dequeued from a queue of packets maintained in a buffer in a network element operating, estimating a current queuing latency for the queue of packets based on the average dequeue rate, determining a target delay based on the average dequeue rate, the target delay varying with the average dequeue rate according to a predetermined relationship, and calculating a current drop probability associated with a probability that packets arriving at the buffer will be dropped or marked, the current drop probability being calculated using at least the current queuing latency and the target delay. In some embodiments, a threshold for a number of bytes dequeued from the buffer is estimated based on network conditions.

Adapting proportional integral controller enhanced algorithm for varying network conditions in a network environment

In one embodiment, a method includes estimating a current queuing latency, the estimated current queuing latency being associated with a queue of packets maintained in a buffer. The method also includes calculating a current drop or mark probability, the current drop or mark probability being associated with a probability that packets associated with the queue of packets will be dropped or marked. A rate at which the packets associated with the queue of packets are dequeued from the buffer is estimated in order to estimate the current queuing latency. The current drop or mark probability is calculated using the current estimated queuing latency.

Utilizing latency control to alleviate bufferbloat

An example method includes sending a virtual output queue (VOQ) length of a VOQ to an egress chip. The VOQ relates to a flow routed through an egress port associated with the egress chip. The method also includes receiving fair share information for the VOQ from the egress chip, and enforcing a control action on the incoming packets based on the fair share information. An ingress chip and the egress chip can be provided in a VOQ switch. The control action is a selected one of a group of actions, the group consisting of: (a) dropping packets, (b) pausing packets, and (c) marking packets. The method can further include receiving VOQ lengths of corresponding VOQs from respective ingress chips, where the VOQs relate to the flow. The method can also include calculating respective fair share information for each VOQ, and sending the fair share information to the respective ingress chips.

System and method for distributed resource control of switches in a network environment

In one embodiment, a method comprises the following steps: receiving a first set of inputs comprising a first plurality of entities and a first traffic behavior; determining a first region of a buffer corresponding to the first traffic behavior; assigning the first plurality of entities to the first region; determining hierarchical relationships between at least some of the first plurality of entities; determining a first shared buffer space of the first region; and assigning at least one threshold for each of the first plurality of entities. The threshold may comprise a maximum amount of the first shared buffer space that may be allocated to an entity. The method may also involve configuring a logic device to allocate the first shared buffer space dynamically according to the hierarchical relationships and the thresholds.

Flexible and hierarchical dynamic buffer allocation

In one embodiment, apparatus and methods for apparatus and methods for fair bandwidth allocation are disclosed. In one embodiment, a method includes (i) determining a drop probability for each of a plurality of classes of packets being dropped or admitted to a queue, wherein each drop probability is based on a weighted fair bandwidth allocation process that is performed with respect to the plurality of classes and a plurality of packet arrival rates and predefined weights for such classes; and (ii) dropping a particular packet or admitting such particular packet to the queue based on the drop probability for such particular packet's class, wherein such dropping or admitting operation is further based on one or more drop precedence factors that are also determined periodically for each class if such one or more drop precedence factors are selected for such each class. In other embodiments, the invention pertains to an apparatus having one or more processors and one or more memory, wherein at least one of the processors and memory are adapted for performing the above described method operations.

Apparatus and methods for hybrid fair bandwidth allocation and drop precedence

Growing community of inventors

San Jose, CA, United States of America

Chiara Piglione