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Hitachi Energy Ltd

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Hitachi Energy Switzerland Ag

Chiara Corvasce

Munaf Rahimo

Arnost Kopta

Luca De-Michielis

Maxi Andenna

Florin Udrea

Liutauras Storasta

Charalampos Papadopoulos

Marina Antoniou

Iulian Nistor

Umamaheswara Vemulapati

Sven Matthias

Thomas Stiasny

Jan Vobecky

Wolfgang Amadeus Vitale

Neophytos Lophitis

Elizabeth Buitrago

Uwe Badstuebner

Manuel Le Gallo

Manuel Le-Gallo

An insulated gate bipolar transistor includes a source electrode, a collector electrode, a source layer, a base layer, a drift layer and a collector layer. Trench gate electrodes extend through the base layer into the drift layer. A channel is located between the source layer, the base layer and the drift layer. A trench Schottky electrode is adjacent to one of the trench gate electrodes and includes an electrically conductive Schottky layer arranged lateral to the base layer and extends through the base layer into the drift layer. The Schottky layer is electrically connected to the source electrode. Collection areas are located in the drift layer at a respective trench gate electrode bottom of the trench gate electrodes or of the trench Schottky electrode. The Schottky layer forms a Schottky contact to the collection area at a contact area.

Insulated gate bipolar transistor including trench Schottky electrode

A power semiconductor device comprises a semiconductor body, a gate electrode, and an extraction electrode, wherein the semiconductor body comprises a source region of a first conductivity type, well region of a second conductivity type different from the first conductivity type at the gate electrode, a drift region which is of the first conductivity type, and a barrier region which is of the first conductivity type, the barrier region is located between the drift region and the extraction electrode.

Power semiconductor device and manufacturiing method

A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells () and a pilot diode unit cell () comprising a second conductivity type anode region () in direct contact with a first main electrode () and extending from a first main side () to a first depth (d). Each active unit cell () comprises a first conductivity type first source layer () in direct contact with the first main electrode (), a second conductivity type base layer () and a first gate electrode (), which is separated from the first source layer () and the second conductivity type base layer () by a first gate insulating layer () to form a first field effect transistor structure. A lateral size (w) of the anode region () in an orthogonal projection onto a vertical plane perpendicular to the first main side () is equal to or less than 1 μm. On a first lateral side surface of the anode region () a first insulating layer () is arranged and on an opposing second lateral side surface of the anode region () a second insulating layer () is arranged. And a distance between the first insulating layer () and the second insulating layer () is equal to or less than 1 μm, the first insulating layer () extending vertically from the first main side () to a second depth (d), and the second insulating layer () extending vertically from the first main side () to a third depth (d), wherein the first depth (d) is less than the second depth (d) and less than the third depth (d).

Reverse conducting insulated gate power semiconductor device having low conduction losses

An insulated gate power semiconductor device (), comprises in an order from a first main side () towards a second main side () opposite to the first main side () a first conductivity type source layer (), a second conductivity type base layer (), a first conductivity type enhancement layer () and a first conductivity type drift layer (). The insulated gate power semiconductor device () further comprises two neighbouring trench gate electrodes () to form a vertical MOS cell sandwiched between the two neighbouring trench gate electrodes (). At least a portion of a second conductivity type protection layer () is arranged in an area between the two neighbouring trench gate electrodes (), wherein the protection layer () is separated from the gate insulating layer () by a first conductivity type channel layer () extending along the gate insulating layer ().

Insulated gate power semiconductor device and method for manufacturing such device

An insulated gate power semiconductor device includes an (n-) doped drift layer between an emitter side and a collector side. A p doped protection pillow covers a trench bottom of a trench gate electrode. An n doped enhancement layer having a maximum enhancement layer doping concentration in an enhancement layer depth separates the base layer from the drift layer. An n doped plasma enhancement layer having a maximum plasma enhancement layer doping concentration covers an edge region between the protection pillow and the trench gate electrode. The N doping concentration decreases from the maximum enhancement layer doping concentration towards the plasma enhancement layer and the N doping concentration decreases from the maximum plasma enhancement layer doping concentration towards the enhancement layer such that the N doping concentration has a local doping concentration minimum between the enhancement layer and the plasma enhancement layer.

Insulated gate power semiconductor device and method for manufacturing such a device

An IGBT is provided with at least two first cells, each of which have an n doped source layer, a p doped base layer, an n doped enhancement layer. The base layer separates the source layer from the enhancement layer, an n-doped drift layer and a p doped collector layer. Two trench gate electrodes are arranged on the lateral sides of the first cell. The transistor includes at least one second cell between the trench gate electrodes of two neighboring first cells, which has on the emitter side a p+ doped well and a further n doped enhancement layer which separates the well from the neighboring trench gate electrodes. An insulator layer stack is arranged on top of the second cell on the emitter side to insulate the second cell and the neighboring trench gate electrodes from the metal emitter electrode.

Insulated gate bipolar transistor

The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 &#x3bc;m from the second plane in a direction towards the wafer.

Power semiconductor device with thick top-metal-design and method for manufacturing such power semiconductor device

An insulated gate power semiconductor device has an (n&#x2212;) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench bottom and trench lateral sides and extends to a trench depth. A p doped first protection pillow covers the trench bottom. An n doped second protection pillow encircles the trench gate electrode at its trench lateral sides. The second protection pillow has a maximum doping concentration in a first depth, which is at least half the trench depth, wherein a doping concentration of the second protection pillow decreases towards the emitter side from the maximum doping concentration to a value of not more than half the maximum doping concentration. An n doped enhancement layer has a maximum doping concentration in a second depth, which is lower than the first depth, wherein the doping concentration has a local doping concentration minimum between the second depth and the first depth.

A reverse-conducting MOS device is provided having an active cell region and a termination region. Between a first and second main side. The active cell region comprises a plurality of MOS cells with a base layer of a second conductivity type. On the first main side a bar of the second conductivity type, which has a higher maximum doping concentration than the base layer, is arranged between the active cell region and the termination region, wherein the bar is electrically connected to the first main electrode. On the first main side in the termination region a variable-lateral-doping layer of the second conductivity type is arranged. A protection layer of the second conductivity type is arranged in the variable-lateral-doping layer, which protection layer has a higher maximum doping concentration than the maximum doping concentration of the variable-lateral-doping layer in a region attached to the protection layer.

Reverse-conducting semiconductor device

A termination region of an IGBT is described, in which surface p-rings are combined with oxide/polysilicon-filled trenches, buried p-rings and surface field plates, so as to obtain an improved distribution of potential field lines in the termination region. The combination of surface ring termination and deep ring termination offers a significant reduction in the amount silicon area which is required for the termination region.

Edge termination for semiconductor devices and corresponding fabrication method

An IGBT is provided having a first gate unit having first trench gates with first conductive layers and planar gates with second conductive layers. A second gate unit having a second trench gates may be connected to the emitter electrode, with the first and second conductive layers forming a first shape closed in itself and enclosing the second gate unit. Third trench gates are arranged between a planar gate and the second gate unit such that first and third trench gates are connected and form a second shape closed in itself by which the second gate unit is enclosed. P+ doped bars below the planar gale contact the emitter electrode with each third trench gate separating a bar and a planar gate electrode from the second gate unit, with a p doped base layer separating the second gate unit from the enclosing second shape.

A Reverse-conducting semiconductor device which comprises a freewheeling diode and an insulated gate bipolar transistor on a common wafer, part of which wafer forms a base layer of a first conductivity type with a first doping concentration and a base layer thickness. The insulated gate bipolar transistor comprises a collector side and an emitter side opposite the collector side of the wafer. A cathode layer of a first conductivity type with at least one first region and a anode layer of a second conductivity type with at least one second and pilot region are alternately arranged on the collector side. Each region has a region area with a region width surrounded by a region border. The Reverse-conducting-IGBT of the present application satisfies a number of specific geometrical rules.

An IGBT has layers between emitter and collector sides, including a drift layer, a base layer electrically contacting an emitter electrode and completely separated from the drift layer, first and second source regions arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and first and second trench gate electrodes. The first trench gate electrodes are separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel is formable between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrodes. An enhancement layer separates the base layer from the drift layer. The second trench gate electrode is separated from the base layer, the enhancement layer and the drift layer by a third insulating layer.

An IGBT has layers between emitter and collector sides. The layers include a collector layer on the collector side, a drift layer, a base layer of a second conductivity type, a first source region arranged on the base layer towards the emitter side, a trench gate electrode arranged lateral to the base layer and extending deeper into the drift layer than the base layer, a well arranged lateral to the base layer and extending deeper into the drift layer than the base layer, an enhancement layer surrounding the base layer so as to completely separate the base layer from the drift layer and the well, an electrically conducting layer covering the well and separated from the well by a second electrically insulating layer, and a third insulating layer having a recess on top of the electrically conducting layer such that the electrically conducting layer electrically contacts a emitter electrode.

An IGBT has layers between emitter and collector sides. The layers include a drift layer, a base layer electrically contacting an emitter electrode and separated from the drift layer, a first source region arranged on the base layer towards the emitter side and electrically contacting the emitter electrode, and a first trench gate electrode arranged lateral to the base layer and separated from the base layer, the first source region and the drift layer by a first insulating layer. A channel exits between the emitter electrode, the first source region, the base layer and the drift layer. A second insulating layer is arranged on top of the first trench gate electrode. An enhancement layer separates the base layer from the drift layer in a plane parallel to the emitter side. A grounded gate electrode includes a second, grounded trench gate electrode and an electrically conducting layer.

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Chiara Corvasce