Micron Technology Incorporated

Chiara Cerafogli

Fulvio Rori

Giuseppe Cariello

Kenneth William Marr

Joshua Daniel Tomayer

Carla L Christensen

James E Davis

Marco Domenico Tiburzi

Lalla Fatima Drissi

Anna Scalesse

Maddalena Calzolari

Iolanda Del Villano

Michael P Violette

Michele Piccardi

Scott Anthony Stoller

Eric Higgins Freeman

Andrea D'Alessandro

Agostino Macerola

Marco-Domenico Tiburzi

Jason Lee Nevill

Jonathan W Oh

Brian J Soderling

Justin Bates

Shannon Marissa Hansen

Fatma Arzum Simsek-Ege

Walter Di Francesco

Pitamber Shukla

Carmine Miccoli

Tawalin Opastrakoon

Carly M Wantulok

Sumana Adusumilli

Sriteja Yamparala

Hope Abigail Henry

Nkiruka Christian

Maithilee Motlag

Ryan Hrinya

Methods, apparatuses, and non-transitory machine-readable media associated with determining a location of an object are described. An object location determination can include receiving a user request associated with an object, receiving first signaling from a first image source, and receiving second signaling from a second image source. The object location determination can include writing data that is based at least in part on a combination of the user request, the first signaling, and the second signaling and determining a confidence level of identification of the object associated with the user request based on the user request, the first signaling, and the second signaling. The object location determination can include identifying output data representative of a location of the object based on the confidence level and transmitting the output data representative of the location of the object via third signaling.

Object location determination

Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

Memory device including circuitry under bond pads

A discharge circuit includes a transistor and a metal resistor connected to the transistor. The transistor includes a plurality of unit cells. The metal resistor includes a plurality of resistor portions corresponding to the plurality of unit cells. Each unit cell of the plurality of unit cells has a footprint and a corresponding resistor portion of the plurality of resistor portions is arranged within the footprint.

Discharge circuits

Methods, systems, and devices for techniques for enhanced read performance on blocks of memory cells are described. The method may involve selecting a first block of memory cells from a set of blocks of memory cells of a memory system based on a condition of the first block of memory cells being met and setting one or more programming parameters corresponding to the first block of memory cells such that the one or more programming parameters are within a threshold value of one or more programming parameters corresponding to a second block associated with a storage density different from a storage density of the first block of memory cells. Further, the method may involve performing an operation on the block of memory cells according to the one or more programming parameters.

Techniques for enhanced read performance on repurposed blocks of memory cells

Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

Techniques for suspend operations

Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

NAND temperature-aware operations

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

Apparatus and method of performing erase and erase verify operations

Various embodiments of the present disclosure relate to monitoring the integrity of power signals within memory systems. A method can include receiving a power signal at a memory component, and monitoring, via a power signal monitoring component of the memory component, an integrity characteristic of the power signal. Responsive to the integrity characteristic meeting a particular criteria, the method can include providing a status indication to a control component external to the memory component.

Power integrity monitoring

Methods, systems, and devices for host-enabled block swap techniques are described. In some examples, a host system may receive an indication of a health metric associated with a first physical block and a second physical block of a memory system, where a first logical block of the memory system is associated with a first type of data and is mapped to the first physical block, and where a second logical block of the memory system is associated with a second type of data. The host system may then determine that the health metric associated with the first physical block satisfies a threshold and may update a mapping associated with the first virtual block, the second virtual block, the first physical block, and the second physical block.

Host-enabled block swap techniques

A microelectronic chip device includes a semiconductor substrate and multiple on-chip strain sensors (OCSSs) constructed on the substrate at various locations of the substrate. The OCSSs may each include multiple piezoresistive devices configured to sense a strain at a location of the various locations and produce a strain signal representing the strain at that location. A strain measurement circuit may also be constructed on the semiconductor substrate and configured to measure strain parameters from the strain signals produced by the OCSSs. The strain parameters represent the strains at the various location. Values of the strain parameters can be used for analysis of mechanical stress on the chip device.

Method and apparatus for on-chip stress detection

A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

Hybrid routine for a memory device

Methods, apparatuses, and non-transitory machine-readable media associated with data transmission are described. Data transmission management can include receiving, from an edge device via a radio at a first device, instructions associated with data transmission between a second device in communication with the first device and a cloud service in communication with the first device. Data transmission management can also include managing, at the first device and based on the instructions from the edge device, data received from a memory resource of the second device for transmission to the cloud service and data received from the cloud service for transmission to the memory resource of the second device. Data transmission management can further include enabling transmission of some, none, or all of the data between the cloud service and the memory resource of the second device and vice versa based on the management of the data.

Data transmission management

Various embodiments provide for adjusting (or adapting) a program voltage step used to program a memory cell by a program algorithm after the program algorithm resumes from a suspension, where the program voltage step is adjusted (or adapted) based on one or more factors.

Program voltage step based on program-suspend time

The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

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Boise, ID, United States of America

Chiara Cerafogli