Industrial Technology Research Institute

Tsinghua University

Chiao-Ling Lung

Shih-Chieh Chang

Jui-Hung Chien

Yung-Fa Chou

Ding-Ming Kwai

Yiyu Shi

Yu-Shih Su

A fault-tolerant unit and a fault-tolerant method for through-silicon via (TSV) are provided. The fault-tolerant unit includes TSV structures TSV&#x2dc;TSVn, nodes N&#x2dc;N, nodes N&#x2dc;Nand a switching module. The TSV structure TSVi is connected between the node Nof the first chip and the node Nof the second chip, wherein 1&#x2266;i&#x2266;n. The switching module is connected between the nodes N&#x2dc;Nof the second chip and a test path of the second chip. In normal operation state, the switching module disconnects the test path and the nodes N&#x2dc;Nwhen the TSV structures TSV&#x2dc;TSVn are valid. The switching module connects the node Nto at least another one of the nodes N&#x2dc;Nwhen the TSV structure TSVi is faulty in the normal operation state. In test status, the switching module connects the test path to the nodes N&#x2dc;N.

Fault-tolerant unit and method for through-silicon via

A semiconductor device stacked structure is disclosed, which includes multiple semiconductor devices and at least one reinforcing structure. The semiconductor devices are stacked on one another. At least one semiconductor device has at least one through silicon via. Each reinforcing structure surrounds a corresponding one of the at least one through silicon via and is electrically insulated from the semiconductor devices. The at least one reinforcing structure includes multiple reinforcing elements and at least one connecting element. Each reinforcing element is disposed between the semiconductor devices. Vertical projections of the reinforcing elements on a plane define a close region, and a projection of the at least one through silicon via on the plane is located within the close region. The connecting element is located in an overlapping region of the vertical projections of the reinforcing elements on the plane, for connecting the reinforcing elements to form the reinforcing structure.

Semiconductor device stacked structure

A stress relief structure is provided. The stress relief structure includes a stress relief body, at least one first stress relief base and at least one second stress relief base. The stress relief body has an upper surface and a lower surface opposite to each other. The first stress relief base is disposed on the upper surface of the stress relief body. The second stress relief base is disposed on the lower surface of the stress relief body. The at least one first stress relief base and the at least one second stress relief base are interlaced to each other.

Stress relief structure

A power-mode-aware (PMA) clock tree and a synthesis method thereof are provided. The clock tree includes a sub clock tree and a PMA buffer. The sub clock tree transmits a delayed clock signal to a function module, wherein a power mode of the function module is determined according to a power information. The PMA buffer is coupled to the sub clock tree. The PMA buffer determines the delay time of a system clock signal according to the power information delays the system clock signal, and outputs the delayed system clock signal to the sub clock tree as the delayed clock signal.

Growing community of inventors

Hsinchu County, Taiwan

Chiao-Ling Lung