Google Inc.

Mentor Graphics Corporation

Other

O-in Design Automation, Inc.

Chian-Min Richard Ho

Ping Fai Yeung

Kalyana C Mulam

Jeffrey Adgate Dean

Azalia Mirhoseini

Anna Darling Goldie

Mustafa Nazim Yazgan

Jeremy Rutledge Levitt

Christophe Gauthron

Ramesh Sathianathan

Tai An Ly

Lawrence Curtis Widdoes, Jr

Jing Chyuarn Lin

Jean-Charles Giomi

Paul Andrew Wilcox

Robert Kristianto Mardjuki

David Lansing Dill

Quoc V Le

James Laudon

Emre Tuncer

Wenjie Jiang

Shen Wang

Roger David Carpenter

Young-Joon Lee

Ebrahim Songhori

Kavya Srinivasa Setty

Omkar Pathak

William Hang

Ya Wang

Anand Babu

Paul Ii Estrada

Paul Estrada, Ii

Paul Il Estrada

James Andrew Garrard Seawright

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip placement. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip placement, comprising placing a respective macro node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the macro node to be placed at the time step to a position from the plurality of positions using the score distribution.

Generating integrated circuit placements using neural networks

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for generating a computer chip floorplan. One of the methods includes obtaining netlist data for a computer chip; and generating a computer chip floorplan, comprising placing a respective node at each time step in a sequence comprising a plurality of time steps, the placing comprising, for each time step: generating an input representation for the time step; processing the input representation using a node placement neural network having a plurality of network parameters, wherein the node placement neural network is configured to process the input representation in accordance with current values of the network parameters to generate a score distribution over a plurality of positions on the surface of the computer chip; and assigning the node to be placed at the time step to a position from the plurality of positions using the score distribution.

Generating integrated circuit floorplans using neural networks

The amount of analysis performed in determining the validity of a property of a digital circuit is measured concurrent with performance of the analysis, and provided as an output when a true/false answer cannot be provided e.g. when stopped due to resource constraints. In some embodiments, a measure of value N indicates that a given property that is being checked will not be violated within a distance N from an initial state from which the analysis started. Therefore, in such embodiments, a measure of value N indicates that the analysis has implicitly or explicitly covered every possible excursion of length N from the initial state, and formally proved that no counter-example is possible within this length N.

Measure of analysis performed in property checking

A programmed computer searches for functional defects in a description of a circuit undergoing functional verification in the following manner. The programmed computer simulates the functional behavior of the circuit in response to a test vector, automatically restores the state of the simulation without causing the simulation to pass through a reset state, and then simulates the functional behavior of the circuit in response to another test vector. A predetermined rule can be used to identify test vectors to be simulated, and the predetermined rule can depend upon a measure of functional verification, including the number of times during simulation when a first state transition is performed by a first-controller at the same time as a second state transition is performed by a second controller. During simulation of the test vectors, manually generated tests or automatically generated checkers can monitor portions of the circuit for defective behavior.

Method for automatically searching for functional defects in a description of a circuit

A computer is programmed to automatically select a state or a set of states of a digital circuit that are visited during simulation, for use as one or more initial states by a formal verification tool. Such automatic selection of one or more simulation states reduces the set of all simulation states to a small subset, thereby to address the state space explosion problem. Depending on the embodiment, the programmed computer uses one or more criteria provided by a library and/or by the user, in making its selection of states. Such criteria may be based on a property (assertion/checker) of the digital circuit and/or a signal generated during simulation. Furthermore, after such criteria (also called 'primary criteria') are applied, the selected states may be pruned by application of additional criteria (also called 'secondary criteria') prior to formal analysis.

Selection of initial states for formal verification

Growing community of inventors

Palo Alto, CA, United States of America

Chian-Min Richard Ho