United Microelectronics Corp.

Chian-Gauh Shih

Hsin-Pang Lu

Jacob Chen

Yanan Mou

Jiunn-Fu Liu

Cheng-Ju Hsieh

Jaris Yeh

A three-dimensional system-on-chip structure comprises a plurality of chips and a plurality of plugs respectively fabricated in the chips. The chips are stacked on top of each other and each includes a periphery circuitry region. A plurality of contact pads is fabricated in each of the periphery circuitry regions. The plugs are formed in the corresponding stacked chips, and are electrically connected to the corresponding contact pads of two of the corresponding chips which are adjacent to each other, or two of the corresponding chips which are not adjacent to each other.

Three-dimensional system-on-chip structure

An input/output circuit with wide voltage tolerance is using a feedback circuit for increasing the voltage tolerance. A single gate oxide structure is fabricated instead of a dual gate oxide structure.

Input and output circuit with wide voltage tolerance

A power source design for embedded memory uses independent power sources such that a first power source group is linked to the DRAM, a second power source group is linked to the logic unit and a third power source group is linked to the testing mode circuit with input/output ports during the silicon chip stage. In the packaging stage the first power source group, the second power source group and the third power source group are joined together. The design is able to prevent testing errors or instability due to direct current from floating nodes in the silicon chip testing stage, and prevent a potential latch-up problem in the packaging stage.

Growing community of inventors

Hsinchu Hsien, Taiwan

Chian-Gauh Shih