Sony Corporation

Sony Semiconductor Solutions Corporation

Other

Chiaki Takano

Toshimasa Shimizu

Akihiko Okubora

Masaru Wada

Hidetoshi Kawasaki

Kevin Fronczak

Kiyoshi Tanaka

Robert James Childs

John Steven Childs

Cody Cziesler

Hirotaka Murakami

Scott A Rogerson

Mark Pude

Robert Justin Jarnot

Hideto Ishikawa

Yuki Takizawa

An imaging device includes a controller, a power supply, a regulator, and a switch. The controller is configured to control an imaging unit, on the basis of a command and data that are received from a host in accordance with an I2C/I3C communication protocol. The power supply is configured to supply a voltage to a digital block of the controller. The digital block is configured to be subjected to dynamic voltage frequency scaling within one-frame operation. The regulator and the switch are provided between the digital block and the power supply, and coupled in parallel with each other.

Imaging device, imaging method, and electronic apparatus

An imaging device includes a controller and a generator. The controller controls an imaging unit on the basis of a command and data received from a host in accordance with an I2C/I3C communication protocol. The generator generates a second control signal indicating whether or not to apply intra-frame dynamic frequency scaling (DFS) or intra-frame dynamic voltage frequency scaling (DVFS) on the basis of a first control signal received from the host via a first route different from the I2C/I3C communication protocol, and outputs the second control signal to the host via a second route different from the I2C/I3C communication protocol.

For suppressing generation of leakage current and side-gate effect in a junction field effect transistor, a gate extension is formed on a semi-insulative compound semiconductor substrate in a manner to extend from a gate and to protrude outward beyond a channel transversely thereto, and an insulating layer is formed on the semi-insulative compound semiconductor substrate under the gate extension. A method of producing this transistor comprises the steps of first forming a channel and a source-drain on a substrate, then forming a gate on the channel together with a gate extension which extends from the gate and protrudes outward beyond the channel transversely thereto, and forming an insulating layer adjacently to the channel and the source-drain in such a manner that no gap is existent between the insulating layer and at least the channel.

Junction field effect transistor and method of producing the same

In a GaAs IC using an E/R type DCFL circuit or E/D type DCFL circuit, a Schottky barrier diode is connected between the positive polarity power source of the DCFL circuit and a load element. A deterioration of switching speed is prevented even in case of using a power source voltage of 2 V in the GaAs IC. Addition of the Schottky barrier diode in a super buffer circuit to prevent a slow increase in output voltage in the circuit is also disclosed.

Super buffer and DCFL circuits with Schottky barrier diode

An optical-electronic integrated circuit device capable of three-dimensionally transmitting optical signals between plural semiconductor substrates on each of which an integrated circuit is previously formed. At least one of the light emitting elements and the light receiving elements are formed on the semiconductor substrate which transmits the light propagated between these elements. In this manner, signals may be transmitted in a direction perpendicular to the semiconductor substrate even without specifically processing the semiconductor substrate. Additionally, signal distortion, transmission losses, mutual intervention or delay are not incurred. For two-dimensionally connecting plural three-dimensionally integrated optical-electronic integrated circuit devices in a direction parallel to the semiconductor substrates, the circuit devices are arrayed on an optical interconnection base plate, and light signals are transmitted by means of a pair of inclined surfaces which are formed on the optical interconnection base plate and which are arranged facing the light emitting element and the light receiving element, and the light waveguide channels defined between these inclined surfaces. This drastically increases the operating speed of the circuit device and the integration degree.

Three-dimensional optical-electronic integrated circuit device with

A semiconductor integrated circuit having a clock signal generator comprising a ring oscillator, a divider, a phase comparator, and an up-down counter. The ring oscillator provides variable oscillation frequencies determined by a sum of the delay times provided by the circuit elements constituting the oscillator. The divider divides the oscillation frequency from the ring oscillator by a specified number. The phase comparator compares the frequency of the signal from the divider with the frequency of the external clock signal. The up-down counter controls the oscillation frequency of the ring oscillator by selectively operating switches connected with the ring oscillator based on the comparison result from the comparator. The clock generator is controlled by an external clock signal to generate an internal clock signal having a higher frequency and outputs both signals. This makes it possible to constitute the semiconductor integrated circuit by using the digital integrated circuit technology alone, thereby allowing the slow operating semiconductors and fast operating semiconductors to exist on the same circuit without sacrificing the excellent characteristics of the latter.

Semiconductor integrated circuit having clock signal generator

A master-slave type flip-flop circuit with first and second transmission gates receives an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and receives a clock signal at a common clock input terminal. A first data holding section includes first and second inverters and first and second resistors cross-connected between input and output terminals of the first and second inverters for receiving outputs of the first and second transmission gates at the input terminals of the first and second inverters. Third and fourth transmission gates receive outputs of the first and second inverters, respectively, of the data holding section and further receive an inverted clock signal at a common inverted clock input terminal. A second holding data section includes third and fourth inverters and third and fourth resistors cross-connected between input and output terminals of the third and fourth inverters fro receiving output of the third and fourth transmission gates at the input terminals of the third and fourth inverters, respectively, The flip-flop circuit is reduced in total number of inverters and hence in power consumption and further reduced in number of inverters on a signal transmission line to permit high-speed operation. Where first to fourth capacitors are connected in parallel to the first to fourth resistors, respectively, the speed of charging and discharging of gate capacity of the transmission gates can be raised to assure a higher maximum operating frequency.

Growing community of inventors

Kanagawa, Japan

Chiaki Takano