Nec Corporation

Ryuji Kobayashi

Chiaki Kumamoto

Reiko Kokubu

Atsuo Mochizuki

Hideo Hayashi

In a multiprocessor system, a table is created for each multitask job in the main memory. The table contains a first memory field for storing a task count value 'm', second memory fields respectively identified by successive task count values for storing data respectively indicating the execution start times of 'm' simultaneously executed tasks, and third memory fields respectively identified by successive task count values for storing the run times of 'm' or more simultaneously executed tasks. In response to the roll-in of a given task, the task count value is incremented by 1, and real time data indicated by a system timer is stored into the second memory field identified by the task count value, allowing the selected task to be processed. At the end of the processing of any task, a difference is derived between real time data indicated by the system timer and an execution start time stored in the second memory field identified by the task count value. The difference is then added to a run time previously stored in the third memory field identified by the task count value, to produce a sum. This sum is stored back into the third memory field overwriting the previous run time. The task count value in the first memory field is decremented by 1 to allow the task to be rolled out. Differences are derived between run times stored in successive third memory fields.

Individual task accounting for multiprocessor systems when executing

In a multiprocessor system, a communication register is partitioned into groups of word storage locations and one of the groups is further partitioned into subgroups associated respectively with the processors. An access controller accesses any groups of the communication register when a system program is being processed and accesses one of the subgroup when a user program is being processed. A write controller is responsive to a test & set instruction of first occurrence from a common bus for assembling a lock work with a data word, a control field and a counter field containing a variable count. The control field of the lock word is set to a first binary state when it is assembled and reset to a second binary state when deassembled. In response to a load instruction from the common bus, either the data word from the bus or lock word is stored into a specified storage area of a communication register. A read controller reads contents of an addressed location of the communication register onto the common bus in response to a save instruction. Test & set instruction of a subsequent occurrence causes the variable count in the stored lock word to be decremented as long as the control field remains set to the first binary state. When the count reduces to zero, a signal is applied to the common bus indicating the occurrence of a dead lock.

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Chiaki Kumamoto