Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Chiaki Kudou

Kunimasa Takahashi

Masahiko Niwayama

Tsutomu Kiyosawa

Masao Uchida

Takashi Hasegawa

Osamu Kusumoto

Kenya Yamashita

Kouichi Saitou

Koichi Hashimoto

Haruyuki Sorada

Masashi Hayashi

Tsuneichiro Sano

Kazuya Utsunomiya

Takayuki Wakayama

Yuki Tomita

Yoshihiro Satou

Ryo Ikegami

A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.

Semiconductor device and method for manufacturing the same

A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, a gate insulating layer, a gate electrode, an interlayer insulating layer, a contact hole, a metal layer, and a source line. The gate electrode is disposed on the gate insulating layer. The interlayer insulating layer covers the gate electrode. The contact hole penetrates the gate insulating layer and the interlayer insulating layer, causes a portion of the surface of the semiconductor substrate to be exposed, and includes an inner surface defined by a side surface of the interlayer insulating layer and a side surface of the gate insulating layer. The metal layer covers an upper surface of the interlayer insulating layer, the inner surface of the contact hole, and at least part of the portion of the surface of the semiconductor substrate exposed by the contact hole.

Semiconductor device and method for manufacturing same

Provided is a silicon carbide semiconductor device that is further reduced in resistance. Silicon carbide semiconductor device includes silicon carbide semiconductor layer disposed on a first main surface of substrate, electrode layer containing polysilicon disposed on the silicon carbide semiconductor layer with first insulating layer interposed between the electrode layer and the silicon carbide semiconductor layer, second insulating layer that covers the silicon carbide semiconductor layer and the electrode layer, first silicide electrode that is located in first opening part formed in the first insulating layer and the second insulating layer and forms ohmic contact with a part of the silicon carbide semiconductor layer, and second silicide electrode that is located in second opening part formed in the second insulating layer and is in contact with a part of the electrode layer.

Silicon carbide semiconductor device and method for manufacturing the same

A silicon carbide semiconductor substrate according to an aspect of the present disclosure has a first principal surface and a second principal surface opposite to the first principal surface. The silicon carbide semiconductor substrate includes a silicon carbide semiconductor crystal, and a first affected layer having crystal disturbances and disposed under the first principal surface. A thickness of the first affected layer in a first region including a center of the first principal surface is smaller than a thickness of the first affected layer in a second region surrounding the first region in a plane view.

Silicon carbide semiconductor substrate used to form semiconductor epitaxial layer thereon

An aspect of the present disclosure resides in a method for manufacturing a compound semiconductor epitaxial substrate including a substrate and a compound semiconductor epitaxial layer disposed on the substrate, the method including providing the substrate, heating a carrier gas, preparing a mixed gas by mixing the heated carrier gas with at least a portion of a source gas that is a source for the compound semiconductor epitaxial layer, the source gas having a lower temperature than the heated carrier gas, and forming the compound semiconductor epitaxial layer on the substrate by supplying the mixed gas onto the substrate.

Method for manufacturing compound semiconductor epitaxial substrates including heating of carrier gas

A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.

Semiconductor device and method for fabricating the same

A semiconductor device includes: a first silicon carbide semiconductor layer; a p-type first impurity region provided in the first silicon carbide semiconductor layer; and a first ohmic electrode forming ohmic contact with the p-type first impurity region. The first ohmic electrode is a silicon alloy containing nitrogen, an average concentration of nitrogen in the first ohmic electrode is higher than or equal to one half of an average concentration of nitrogen in the first impurity region, and an average concentration of a p-type impurity in a portion of the first ohmic electrode except a portion of the first ohmic electrode within 50 nm from an interface between the first ohmic electrode and the first impurity region is equal to or lower than 3.0&#xd7;10cm.

Silicon carbide semiconductor device having nitrogen-containing silicon alloy for ohmic contact to P-type impurity region

This silicon carbide semiconductor device includes: a substrate with a principal surface; a silicon carbide layer which is arranged on a side of the principal surface of the substrate and which includes a first impurity region of a first conductivity type; a trench which is arranged in the silicon carbide layer and which has a bottom located in the first impurity region; a trench bottom impurity layer which is arranged in the trench to contact with at least a portion of the bottom of the trench and which is a silicon carbide epitaxial layer of a second conductivity type; a gate insulating film which covers a side surface of the trench and the trench bottom impurity layer; and a gate electrode which is arranged over at least a portion of the gate insulating film that is located inside the trench.

Silicon carbide semiconductor device and method for manufacturing same

A semiconductor device of the present disclosure includes a semiconductor layer provided on a main surface of a substrate. A cell region is provided with a gate insulating film disposed on the semiconductor layer and a gate electrode disposed on the gate insulating film, and a wiring region is provided with a field insulating film disposed on the semiconductor layer and a gate wire disposed on the field insulating film. An end of the field insulating film has a convex shape in a cross section perpendicular to the main surface of the substrate, and an upper surface of the field insulating film is rougher than an upper surface of a portion of the gate wire below which the field insulating film is not disposed.

Semiconductor device having gate wire disposed on roughened field insulating film

A method for manufacturing a semiconductor device includes the steps of: forming, on a principal face of a substrate, a semiconductor layer including a first semiconductor region of a first conductivity type; and forming, in the semiconductor layer, a trench having a bottom located in the first semiconductor region. The method further includes a step of forming a trench bottom impurity region being of a second conductivity type and covering the bottom of the trench by performing annealing to cause part of the semiconductor layer corresponding to an upper corner portion of the trench to move to be placed on the bottom of the trench.

A first first-conductivity-type impurity region () is provided in an upper portion of a semiconductor layer () around a trench (). A gate electrode () is provided on a sidewall surface of the trench (), and on the semiconductor layer () around the trench () with a gate insulating film () interposed therebetween. A second-conductivity-type impurity region () and a second first-conductivity-type impurity region () are interposed between a portion of the gate electrode () around the trench () and the first first-conductivity-type impurity region () sequentially on the first first-conductivity-type impurity region ().

Semiconductor device and method of manufacturing the device

A fabrication method for a semiconductor device includes the step of forming a gate insulating film on the side of a trench, the bottom thereof, and the periphery thereof. The step of forming a gate insulating film includes a step of forming a first insulating film on the side of the trench and a step of forming a second insulating film on the bottom and periphery of the trench using a high-density plasma chemical vapor deposition method. The thickness of the portions of the gate insulating film formed on the bottom and periphery of the trench is made larger than that of the portion of the gate insulating film formed on the side of the trench.

Semiconductor device and fabrication method for the same

A semiconductor deviceincludes: a first silicon carbide layerarranged on the principal surface of a semiconductor substrate; a first impurity regionof a first conductivity type arranged in the first silicon carbide layer; a body regionof a second conductivity type; a contact regionof the second conductivity type which is arranged at a position in the body region that is deeper than the first impurity regionand which contains an impurity of the second conductivity type at a higher concentration than the body region; a drift regionof the first conductivity type; and a first ohmic electrodein ohmic contact with the first impurity regionand the contact region, wherein: a contact trench, which penetrates through the first impurity region, is provided in the first silicon carbide layer; and the first ohmic electrodeis arranged in the contact trenchand is in contact with the contact regionon at least a portion of a side wall lower portionL and a bottom surfaceof the contact trench.

Semiconductor device and process for production thereof

A semiconductor device according to an embodiment of the present invention includes: a semiconductor layerof a wide band gap semiconductor arranged on a principal surface of a substrate; a trencharranged in the semiconductor layer and including a bottom surface, a plurality of main side surfaces, and a plurality of corner side surfaces each connecting together two adjacent main side surfaces; a gate insulating filmarranged on the bottom surface, the main side surfaces and the corner side surfaces of the trench; and a gate electrodearranged in the trench, wherein the semiconductor layer includes a drift regionof a first conductivity type, and a body regionof a second conductivity type arranged on the drift region; the trench runs through the body regionand has the bottom surface inside the drift region; the corner side surfaces of the trench do not have a depressed portion; the gate insulating filmis thicker on the corner side surfaces of the trench than on the main side surfaces of the trench; and a portion of the gate insulating filmthat is located on the corner side surfaces is a first insulating layer, and a portion of the gate insulating filmthat is located on the main side surfaces is a second insulating layer

Semiconductor device and method for producing same

This silicon carbide semiconductor element includes: a body region of a second conductivity type which is located on a drift layer of a first conductivity type; an impurity region of the first conductivity type which is located on the body region; a trench which runs through the body region and the impurity region to reach the drift layer; a gate insulating film which is arranged on surfaces of the trench; and a gate electrode which is arranged on the gate insulating film. The surfaces of the trench include a first side surface and a second side surface which is opposed to the first side surface. The concentration of a dopant of the second conductivity type is higher at least locally in a portion of the body region which is located beside the first side surface than in another portion of the body region which is located beside the second side surface.

Growing community of inventors

Hyogo, Japan

Chiaki Kudou