Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Chiaki Kudo

Hisashi Ogawa

Takashi Nakabayashi

Takaaki Ukeda

Toshiki Yabu

Hiroshi Yamamoto

Junji Hirase

Shinichi Imai

Ichiro Nakao

Yuka Terai

Yasushi Naito

Toyokazu Fujii

Kazuhiko Aida

Takatoshi Yasui

Akihiro Yamamoto

A semiconductor device includes: an isolation region formed in a semiconductor substrate; an active region surrounded by the isolation region; and a first gate electrode formed on the isolation region and the active region and including a first region on the isolation region. The first region has a pattern width in a gate length direction larger than a pattern width of the first gate electrode on the active region. The first region includes a part having a film thickness different from a film thickness of the first gate electrode on the active region.

Semiconductor device and manufacturing method thereof

When charges Q (x, y) transferred from an image inputting deviceare to be converted into first signal intensities S' (x, y) and signal processing is to be performed for the first signal intensity S&#x2032; (x, y) of a particular pixel, a maximum value Smax, a minimum value Smin and an average value Save are calculated from signal intensities S&#x2032; (x&#x2212;1, y) and S&#x2032; (x+1, y) at adjacent pixels. When S&#x2032; (x, y)&#x3e;Smax&#xd7;A is satisfied, it is determined that the signal intensity S (x, y) at the particular pixel=Save&#xd7;C (where A and C are coefficients), whereas when S&#x2032; (x, y)&#x3c;Smin&#xd7;B is satisfied, it is determined that the signal intensity S (x, y)=Save&#xd7;D (where B and D are coefficients), and processing is performed so as to obtain an appropriate intensity S (x, y). This makes it possible to accurately judge a defective pixel attributable to dirt adhering to a pixel array of the image inputting device, a crystal defect, etc., and compensate a defect in an image caused by the defective pixel.

Method and apparatus for correcting pixel image signal intensity

The following steps are carried out: forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween, forming a dummy gate electrode on the semiconductor substrate with a dummy gate insulating film interposed therebetween and forming another dummy gate electrode on the semiconductor substrate with an insulating film for isolation interposed therebetween; forming a metal film on the semiconductor while exposing the gate electrode and covering the dummy gate electrodes; and subjecting the semiconductor substrate to heat treatment and thus siliciding at least an upper part of the gate electrode. Since the gate electrode is silicided and the dummy gate electrodes are non-silicided, this restrains a short circuit from being caused between the gate electrode and adjacent one of the dummy gate electrodes.

Semiconductor device

In an interconnection mask pattern generation, there are suppressed a decrease in reliability of an interconnection and a decrease in manufacture yield, which are resulted from use of an interconnection pattern generated with single minimum line width data for a semiconductor device or the like. When a layout interconnection pattern on a mask for an interconnection which connects functional elements to each other being arranged based on logical circuit data is generated, an interconnection pattern based on the minimum line width data is generated, an interconnection pattern based on the minimum line spacing data is also generated, and an interconnection pattern arranging a new interconnection boundary in the middle of both of them is then generated to be used as a final interconnection pattern, so that the interconnection pattern width becomes properly thick in width, thereby making it possible to improve reliability of the interconnection and suppress a decrease in manufacturing yield.

Method of generating interconnection pattern

On a semiconductor substrate of P-type silicon, an active area including a channel forming region with a smaller dimension along the gate width and a source region and a drain region extending along the gate length is formed so as to be surrounded with an isolation area of an insulating oxide film. On the isolation area on the semiconductor substrate and the channel forming region of the active area, a gate electrode is formed with a gate insulating oxide film sandwiched therebetween. A channel lower insulating layer is formed, out of the same insulating oxide film for the isolation area, merely in an area below the channel forming region below the gate electrode in the active area of the semiconductor substrate.

Semiconductor device, and semiconductor integrated device

The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the interlayer insulating film. What results is a semiconductor device having lower total wiring-to-substrate capacitance and a higher operating speed.

Trench isolated semiconductor device

The top surface of a P-type semiconductor substrate is partitioned into an active region to be formed with an element and an isolation region surrounding the active region. The isolation region is composed of trench portions and dummy semiconductor portions. An interlayer insulating film is deposited on the substrate, followed by a wire formed thereon. In each of the semiconductor portions, an impurity diffusion layer is formed simultaneously with the implantation of ions into the element so that a PN junction is formed between the impurity diffusion layer and the silicon substrate. A capacitance component of the wiring-to-substrate capacitance in the region containing the semiconductor portions is obtained by adding in series the capacitance in the impurity diffusion layer to the capacitance in the interlayer insulating film, which is smaller than the capacitance only in the inter layer insulating film. What results is a semiconductor device having lower total wiring to-substrate capacitance and a higher operating speed.

Method of manufacturing trench-isolated semiconductor device

Method of manufacturing a semiconductor apparatus having a

A MOS capacitor has a p-type silicon substrate, an n-type impurity diffusion area formed by implanting an impurity into a region of the silicon substrate, a silicon oxide layer formed on the diffusion area, and a polysilicon electrode formed on the silicon oxide layer. An impurity profile is formed in the region such that the concentration of the impurity increases from a surface common to the diffusion area and the silicon oxide layer towards the inside of the silicon substrate. The concentration of the impurity at the interface is less than or equal to 1.times.10.sup.20 cm.sup.-3, and a peak concentration lies at a depth of more than 0.05 .mu.m under the interface. This controls accelerated oxidization during the thermal oxidization and also controls the dependence of the capacitance on the voltage.

MOS capacitor and MOS capacitor fabrication method

Described is a method for manufacturing semiconductor devices which includes a heat treating process for heating and cooling semiconductor substrates mounted on a boat at a predetermined pitch according to a predetermined temperature profile, in order to flatten the surface of each semiconductor substrate by reflowing an insulating film containing impurities, for example, a BPSG film formed on the substrate. In the heat treating process, one of the control factors which affects the formation of grains or particles due to the impurities contained in the insulating film is set so as to prevent the impurities from generating grains or particles during the heat treatment. Also disclosed is a method of preventing the generation of grains or particles by widening the pitch of the mounted substrates.

Growing community of inventors

Amagasaki, Japan

Chiaki Kudo